CENTRE FOR FORMAL DESIGN AND VERIFICATION OF SOFTWARE INDIAN INSTITUTE OF TECHNOLOGY, BOMBAY

CENTRE FOR FORMAL DESIGN AND

VERIFICATION OF SOFTWARE

INDIAN INSTITUTE OF TECHNOLOGY, BOMBAY

Verification & Validation (V&V)

Computer Hardware and Software key component in modern automotives

Safety-critical Systems Rigorous Verification and Validation

Essential ISO/IEC Standards Guidelines MISRA Standards

Bugs are costly Pentium bug

Intel Pentium chip, released in 1994 produced error in floating point division

Cost : $475 million

ARIANE Failure In December 1996, the Ariane 5 rocket exploded 40

seconds after take off . A software components threw an exception

Cost : $400 million payload.

Therac-25 Accident : A software failure caused wrong dosages of x-rays. Cost: Human Loss.

Rigorous V&V Essential

Traditional V & V

Industrial Practices far from satisfactory Testing, Simulation, Reviews & Walkthroughs Inadequate for safety-critical systems Late Detection of bugs Detects presence of bugs not absence When to stop testing

Coverage criteria ~70% of time spent on V&V

Mission of CFDVS

Resources

R & D

V & V Ed.&Tr.

The Mission To Enable, through R&D of new tools and Techniques, to Support through external projects,

to Educate to develop skill base through courses & workshops

to Develop Resource Base of tools,

technologies,standards

RIGOROUS DESIGN, V & V PRACTICES

CFDVS Focus Area V & V based on Formal Methods Safety-critical Systems Hardware & Software Industrial Solutions

Formal Verification More rigorous approach Founded on Mathematical methods Proves correctness of Systems Increased confidence Early Detection of bugs

Design Verification Complementary to traditional

techniques

CFDVS – An R&D Centre Research Projects Case-studies New Tools Efficient Techniques and Novel Design

Methodologies

CFDVS R&D Overview Case-studies Tools

ACE TSCheck ConSDE VE-DAC EX-PERT

Research Papers and Reports

ACE – Assertion checker Assertion-checking tool for formal

verification of MISRA-C Programs Translates C functions plus assertions

to SPL and specifications Verification of SPL programs STeP – Verification Engine Tool extensively used in ADA project

Formal Verification of Flight Software:Sponsor : ADA , Bangalore Validation of software in LCA display unit Verification focused on a collection of C-

functions In house tool ACE extensively used (jointly

developed with BARC) Verification engine : STeP Verification uncovered a few bugs leading to

code revision Designers convinced of utility of FV

Verification of LV Software LV – Launch Vehicle Sponsored by VSSC, Trivandrum Signal integrity checking Complex sequence of branches Code in Ada In-house tool ACE used

CFDVS – A Resource Centre Specification & Verification Tools Academic & Commercial Tools Books, Papers & Reports Hardware & Software support V&V Expert consultancy National Centre

Resources

Hardware : Dec Alpha server Sun server Sun-Fire 280R Many access stations

Software: Formal Check: Hardware Verification Tool(Cadence

Inc.) LDRA : Static analysis tool Rose RT and Rhapsody : UML based tools Esterel Studio and SCADE Specman: Hardware Verification tool Code Surfer: Slicing tool

Resources (contd.)

Books : More than hundred books/proceedings CAV, FMCAD, CHARME

CFDVS – An Educational Centre

Education & Training Courses & Seminars Workshops & Conferences Student Projects & Case studies

Education and Training Attracted many students across different

departments (CSE,IT,EE,Rel. Engg.) Around 30 students (B.Tech and M.Tech)

completed More than 10 students currently working Two BARC staff on deputation Two workshops

Well-attended People from DAE and other organization

Tutorials in international conferences

Industry Sponsored Projects IV & V services Two projects completed Two more projects in Progress Looking forward to more Means of Resource Generation

Verification of Cache controllers

Sponsor : Texas Instruments, Bangalore

Verification using Model Checking of medium sized industrial design.

Cache controller developed at TI, FormalCheck of Cadence Inc. - verifier

Verification of In-house ASICs

Sponsor : BARC Various ASICs designed at BARC Verification of one of these Project in the initial stages

Case-Studies FV of Two Systems from BARC FV of a PCI implementation

FV of PCI implementation Understand issues involved in large hardware

design Evaluate the performance of state-of-the art

tools PCI implementation (10,000 lines of VHDL

code) The tool Formal Check used Models for environment designed Properties formalized in FQL

Design Environment for Process Control Software

ConSDE: A tool for designing process control software from high level block diagrams

A graphical editor A block definition language Code generation from blocks Simulation capabilities Verification capabilities planned

Verification Environment for distributed Control Applications

VE-DAC and EX-PERT: Tool for verification of distributed reactive applications.

State machine based language Capabilities to design concurrent and

hierarchical design Asynchronous communication Editor, simulator and verifier Efficient verification using slicing techniques

. . . And many more Projects Efficient Verification of Synchronous

Programs Model-based Verification of Object-

Oriented Software Slicing of Synchronous Programs and

HDLs