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Cache Memories. Cache Memories. Cache memory organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality. Cache Memories. Cache memories are small, fast SRAM-based memories managed automatically in hardware. - PowerPoint PPT Presentation
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Seoul National University
Cache Memories
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Seoul National University
Cache Memories Cache memory organization and operation Performance impact of caches
The memory mountain Rearranging loops to improve spatial locality
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Seoul National University
Cache Memories Cache memories are small, fast SRAM-based memories
managed automatically in hardware. Hold frequently accessed blocks of main memory
CPU looks first for data in caches (e.g., L1, L2, and L3), then in main memory.
Typical system structure:
Mainmemory
I/Obridge
Bus interface
ALU
Register file
CPU chip
System bus Memory bus
Cache memories
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Seoul National University
General Cache Organization (S, E, B)E = 2e lines per set
S = 2s sets
set
line
0 1 2 B-1tagv
B = 2b bytes per cache block (the data)
Cache size:C = S x E x B data bytes
valid bit
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Seoul National University
Cache ReadE = 2e lines per set
S = 2s sets
0 1 2 B-1tagv
valid bitB = 2b bytes per cache block (the data)
t bits s bits b bitsAddress of word:
tag setindex
blockoffset
data begins at this offset
• Locate set• Check if any line in set
has matching tag• Yes + line valid: hit• Locate data starting
at offset
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Seoul National University
Example: Direct Mapped Cache (E = 1)
S = 2s sets
Direct mapped: One line per setAssume: cache block size 8 bytes
t bits 0…01 100Address of int:
0 1 2 7tagv 3 654
0 1 2 7tagv 3 654
0 1 2 7tagv 3 654
0 1 2 7tagv 3 654
find set
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Seoul National University
Example: Direct Mapped Cache (E = 1)Direct mapped: One line per setAssume: cache block size 8 bytes
t bits 0…01 100Address of int:
0 1 2 7tagv 3 654
match: assume yes = hitvalid? +
block offset
tag
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Seoul National University
Example: Direct Mapped Cache (E = 1)Direct mapped: One line per setAssume: cache block size 8 bytes
t bits 0…01 100Address of int:
0 1 2 7tagv 3 654
match: assume yes = hitvalid? +
int (4 Bytes) is here
block offset
No match: old line is evicted and replaced
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Seoul National University
Direct-Mapped Cache SimulationM=16 byte addresses, B=2 bytes/block, S=4 sets, E=1 Blocks/set
Address trace (reads, one byte per read):0 [00002], 1 [00012], 7 [01112], 8 [10002], 0 [00002]
xt=1 s=2 b=1
xx x
0 ? ?v Tag Block
miss
1 0 M[0-1]
hitmiss
1 0 M[6-7]
miss
1 1 M[8-9]
miss
1 0 M[0-1]Set 0Set 1Set 2Set 3
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Seoul National University
A Higher Level Exampleint sum_array_rows(double a[16][16]){ int i, j; double sum = 0;
for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum;}
32 B = 4 doubles
assume: cold (empty) cache,a[0][0] goes here
int sum_array_cols(double a[16][16]){ int i, j; double sum = 0;
for (j = 0; j < 16; j++) for (i = 0; i < 16; i++) sum += a[i][j]; return sum;}
Ignore the variables sum, i, j
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Seoul National University
E-way Set Associative Cache (Here: E = 2)E = 2: Two lines per setAssume: cache block size 8 bytes
t bits 0…01 100Address of short int:
0 1 2 7tagv 3 654 0 1 2 7tagv 3 654
0 1 2 7tagv 3 654 0 1 2 7tagv 3 654
0 1 2 7tagv 3 654 0 1 2 7tagv 3 654
0 1 2 7tagv 3 654 0 1 2 7tagv 3 654
find set
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Seoul National University
E-way Set Associative Cache (Here: E = 2)E = 2: Two lines per setAssume: cache block size 8 bytes
t bits 0…01 100Address of short int:
0 1 2 7tagv 3 654 0 1 2 7tagv 3 654
compare both
valid? + match: yes = hit
block offset
tag
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Seoul National University
E-way Set Associative Cache (Here: E = 2)E = 2: Two lines per setAssume: cache block size 8 bytes
t bits 0…01 100Address of short int:
0 1 2 7tagv 3 654 0 1 2 7tagv 3 654
compare both
valid? + match: yes = hit
block offset
short int (2 Bytes) is here
No match: • One line in set is selected for eviction and replacement• Replacement policies: random, least recently used (LRU), …
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Seoul National University
2-Way Set Associative Cache Simulation
M=16 byte addresses, B=2 bytes/block, S=2 sets, E=2 blocks/set
Address trace (reads, one byte per read):0 [00002], 1 [00012], 7 [01112], 8 [10002], 0 [00002]
xxt=2 s=1 b=1
x x
0 ? ?v Tag Block
0
00
miss
1 00 M[0-1]
hitmiss
1 01 M[6-7]
miss
1 10 M[8-9]
hit
Set 0
Set 1
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Seoul National University
A Higher Level Exampleint sum_array_rows(double a[16][16]){ int i, j; double sum = 0;
for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum;}
32 B = 4 doubles
assume: cold (empty) cache,a[0][0] goes here
int sum_array_rows(double a[16][16]){ int i, j; double sum = 0;
for (j = 0; j < 16; j++) for (i = 0; i < 16; i++) sum += a[i][j]; return sum;}
Ignore the variables sum, i, j
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Seoul National University
What about writes? Multiple copies of data exist:
L1, L2, Main Memory, Disk What to do on a write-hit?
Write-through (write immediately to memory) Write-back (defer write to memory until replacement of line)
Need a dirty bit (line different from memory or not) What to do on a write-miss?
Write-allocate (load into cache, update line in cache) Good if more writes to the location follow
No-write-allocate (writes immediately to memory) Typical
Write-through + No-write-allocate Write-back + Write-allocate
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Seoul National University
A Common Framework for Memory Hierarchies
Question 1: Where can a Block be Placed? One place (direct-
mapped), a few places (set associative), or any place (fully
associative)
Question 2: How is a Block Found? Indexing (direct-mapped),
limited search (set associative), full search (fully associative)
Question 3: Which Block is Replaced on a Miss? Typically LRU or
random
Question 4: How are Writes Handled? Write-through or write-
back
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Seoul National University
Intel Core i7 Cache Hierarchy
Regs
L1 d-cache
L1 i-cache
L2 unified cache
Core 0
Regs
L1 d-cache
L1 i-cache
L2 unified cache
Core 3
…
L3 unified cache(shared by all cores)
Main memory
Processor package
L1 i-cache and d-cache:32 KB, 8-way, Access: 4 cycles
L2 unified cache: 256 KB, 8-way, Access: 11 cycles
L3 unified cache:8 MB, 16-way,Access: 30-40 cycles
Block size: 64 bytes for all caches.
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Seoul National University
Cache Performance Metrics Miss Rate
Fraction of memory references not found in cache (misses / accesses)= 1 – hit rate
Typical numbers (in percentages): 3-10% for L1 can be quite small (e.g., < 1%) for L2, depending on size, etc.
Hit Time Time to deliver a line in the cache to the processor
includes time to determine whether the line is in the cache Typical numbers:
1-2 clock cycle for L1 5-20 clock cycles for L2
Miss Penalty Additional time required because of a miss
typically 50-200 cycles for main memory (Trend: increasing!)
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Seoul National University
Lets think about those numbers Huge difference between a hit and a miss
Could be 100x, if just L1 and main memory
Would you believe 99% hits is twice as good as 97%? Consider:
cache hit time of 1 cyclemiss penalty of 100 cycles
Average access time: 97% hits: 1 cycle + 0.03 * 100 cycles = 4 cycles 99% hits: 1 cycle + 0.01 * 100 cycles = 2 cycles
This is why “miss rate” is used instead of “hit rate”
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Seoul National University
Writing Cache Friendly Code Make the common case go fast
Focus on the inner loops of the core functions
Minimize the misses in the inner loops Repeated references to variables are good (temporal locality) Stride-1 reference patterns are good (spatial locality)
Key idea: Our qualitative notion of locality is quantified through our understanding of cache memories.
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Seoul National University
Cache Memories Cache organization and operation Performance impact of caches
The memory mountain Rearranging loops to improve spatial locality
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Seoul National University
The Memory Mountain Read throughput (read bandwidth)
Number of bytes read from memory per second (MB/s)
Memory mountain: Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance.
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Seoul National University
Memory Mountain Test Function/* The test function */void test(int elems, int stride) { int i, result = 0; volatile int sink;
for (i = 0; i < elems; i += stride)result += data[i];
sink = result; /* So compiler doesn't optimize away the loop */}
/* Run test(elems, stride) and return read throughput (MB/s) */double run(int size, int stride, double Mhz){ double cycles; int elems = size / sizeof(int);
test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, 0); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* convert cycles to MB/s */}
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Seoul National University
The Memory Mountains1 s3 s5 s7 s9
s11
s13
s15
s32
0
1000
2000
3000
4000
5000
6000
7000
64M 16M 4M 1M 256K
64K 16K 4K
Stride (x8 bytes)
Re
ad
th
rou
gh
pu
t (M
B/s
)
Working set size (bytes)
Intel Core i732 KB L1 i-cache32 KB L1 d-cache256 KB unified L2 cache8M unified L3 cache
All caches on-chip
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Seoul National University
The Memory Mountains1 s3 s5 s7 s9
s11
s13
s15
s32
0
1000
2000
3000
4000
5000
6000
7000
64M 16M 4M 1M 256K
64K 16K 4K
Stride (x8 bytes)
Re
ad
th
rou
gh
pu
t (M
B/s
)
Working set size (bytes)
Intel Core i732 KB L1 i-cache32 KB L1 d-cache256 KB unified L2 cache8M unified L3 cache
All caches on-chip
Slopes ofspatial locality
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Seoul National University
The Memory Mountains1 s3 s5 s7 s9
s11
s13
s15
s32
0
1000
2000
3000
4000
5000
6000
7000
64M 16M 4M 1M 256K
64K 16K 4K
Stride (x8 bytes)
Re
ad
th
rou
gh
pu
t (M
B/s
)
Working set size (bytes)
L1
L2
Mem
L3
Intel Core i732 KB L1 i-cache32 KB L1 d-cache256 KB unified L2 cache8M unified L3 cache
All caches on-chip
Slopes ofspatial locality
Ridges of Temporal locality
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Seoul National University
Cache Memories Cache organization and operation Performance impact of caches
The memory mountain Rearranging loops to improve spatial locality
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Seoul National University
Miss Rate Analysis for Matrix Multiply Assume:
Line size = 32B (big enough for four 64-bit words) Matrix dimension (N) is very large
Approximate 1/N as 0.0 Cache is not even big enough to hold multiple rows
Analysis Method: Look at access pattern of inner loop
A
k
i
B
k
j
C
i
j
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Seoul National University
Matrix Multiplication Example Description:
Multiply N x N matrices O(N3) total operations N reads per source
element N values summed per
destination but may be able to
hold in register
/* ijk */for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; }}
Variable sumheld in register
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Seoul National University
Layout of C Arrays in Memory (review) C arrays allocated in row-major order
each row in contiguous memory locations Stepping through columns in one row:
for (i = 0; i < N; i++)sum += a[0][i];
accesses successive elements if block size (B) > 4 bytes, exploit spatial locality
compulsory miss rate = 4 bytes / B Stepping through rows in one column:
for (i = 0; i < n; i++)sum += a[i][0];
accesses distant elements no spatial locality!
compulsory miss rate = 1 (i.e. 100%)
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Seoul National University
Matrix Multiplication (ijk)
/* ijk */for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; }}
A B C(i,*)
(*,j)(i,j)
Inner loop:
Column-wise
Row-wise Fixed
Misses per inner loop iteration:A B C0.25 1.0 0.0
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Seoul National University
Matrix Multiplication (jik)
/* jik */for (j=0; j<n; j++) { for (i=0; i<n; i++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum }}
A B C(i,*)
(*,j)(i,j)
Inner loop:
Row-wise Column-wise
Fixed
Misses per inner loop iteration:A B C0.25 1.0 0.0
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Seoul National University
Matrix Multiplication (kij)
/* kij */for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; }}
A B C(i,*)
(i,k) (k,*)
Inner loop:
Row-wise Row-wiseFixed
Misses per inner loop iteration:A B C0.0 0.25 0.25
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Seoul National University
Matrix Multiplication (ikj)
/* ikj */for (i=0; i<n; i++) { for (k=0; k<n; k++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; }}
A B C(i,*)
(i,k) (k,*)
Inner loop:
Row-wise Row-wiseFixed
Misses per inner loop iteration:A B C0.0 0.25 0.25
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Seoul National University
Matrix Multiplication (jki)
/* jki */for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; }}
A B C
(*,j)(k,j)
Inner loop:
(*,k)
Column-wise
Column-wise
Fixed
Misses per inner loop iteration:A B C1.0 0.0 1.0
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Seoul National University
Matrix Multiplication (kji)
/* kji */for (k=0; k<n; k++) { for (j=0; j<n; j++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; }}
A B C
(*,j)(k,j)
Inner loop:
(*,k)
FixedColumn-wise
Column-wise
Misses per inner loop iteration:A B C1.0 0.0 1.0
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Seoul National University
Summary of Matrix Multiplication
ijk (& jik): • 2 loads, 0 stores• misses/iter = 1.25
kij (& ikj): • 2 loads, 1 store• misses/iter = 0.5
jki (& kji): • 2 loads, 1 store• misses/iter = 2.0
for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; }}
for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; }}
for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; }}
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Seoul National University
Core i7 Matrix Multiply Performance
50 100 150 200 250 300 350 400 450 500 550 600 650 700 7500
10
20
30
40
50
60
jkikjiijkjikkij
Array size (n)
Cyc
les
per
in
ner
lo
op
ite
rati
on
jki / kji
ijk / jik
kij / ikj
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Seoul National University
Summary Memory hierarchies are an optimization resulting from a perfect
match between memory technology and two types of program locality Temporal locality Spatial locality
The goal is to provide a “virtual” memory technology (an illusion) that has an access time of the highest-level memory with the size and cost of the lowest-level memory
Cache memory is an instance of a memory hierarchy exploits both temporal and spatial localities direct-mapped caches are simple and fast but have higher miss rates set-associative caches have lower miss rates but are complex and slow multilevel caches are becoming increasingly popular
Programmer can optimize for cache performance How data structure are organized How data are accessed (nested loop structure)
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