Built-in Adaptive Test and Calibration of DAC Wei Jiang and Vishwani D. Agrawal Electrical and...

Built-in Adaptive Test and Calibration of DAC

Wei Jiang and Vishwani D. AgrawalElectrical and Computer EngineeringAuburn University, Auburn, AL 36849

18th IEEE North Atlantic Test Workshop 2009

Outline

• Overview

• Previous Work

• Proposed BIST Scheme

• Adaptive Self-Calibration of DAC

• Simulation Results

• Conclusion

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Overview

• Proposed design-for-testability (DFT) architecture for a mixed-signal SoC– Accuracy– Performance– Cost

• Test of on-chip DAC and ADC– Linearity (DNL/INL)– Resolution and speed– Signal-to-noise ratio (SNR)

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A Typical Mixed-Signal BIST for SoC*

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TPG

ORA

TEST CONTROL

MUX

MUX

DAC

ADC

MIXED SIGNAL

MUX

ANALOG SYSTEM

ANALOG SYSTEM

MUX

BIST Results

Digital System

Input and Output

Analog System

Input and

Output

Analog Loopbacks

DSP

DIGITAL SYSTEM

* F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.

DAC

ADC

ANALOG SYSTEM

ANALOG SYSTEM

Analog System

Input and

Output

DSP

DIGITAL SYSTEM

Digital System

Input and

Output

MIXED SIGNAL

Digital non-linearity error

Analog non-linearity error

Previous Work

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W. Jiang and V.D. Agrawal, Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC, NATW’08

Analog input

Dig

ital c

ode

outp

ut

Ideal

Actual (νK)

Ideal

Actual (νK)

Ana

log

outp

ut

Digital code input

Non-linearity error of ADC Non-linearity error of DAC

k

kν

ν

Non-linearity Errors

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Non-linearity error

Non-linearityerror

Proposed BIST Scheme

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DSP

TPG

ORA

MIXED SIGNAL Polynomial coefficients for DAC

x

yAnalog

correction signal Polynomial eval

Digital outputCorrected analog output

Analog loopback

DACunder-test

d-DAC

Measuring ADC

Proposed BIST Scheme (Cont.)• DSP for BIST control

• Components– 1-bit first-order sigma-delta modulator– Low-pass filter (integrator or comb filter)– Adaptive polynomial evaluation/fix circuit– Low-resolution dithering DAC– Loop-back circuitry connecting internal DAC

and ADC

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Testing and characterization of DAC

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DSP

TPG

ORA

MIXED SIGNAL Polynomial coefficients for DAC

0/1

Analog responses

Analog loopback

N-bit

N’-bit

DACunder-test

Low-pass Filter

First-order 1-bit sigma-delta modulator

Testing of DAC (Cont.)

• Response and ramp input compared for INL error

• INL error analyzed by adaptive polynomial fitting algorithm

• Best matching polynomials selected for various and DAC profiles

• Test results indicated by calculated characteristics (offset, gain and harmonic distortion, etc)

• Polynomial coefficients calculated for dithering DAC to improve INL

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Polynomial Fitting• Introduced by Sunter et al. in

ITC’97 and A. Roy et al. in ITC’02

• Summary:– Divide DAC transfer

function into four sections– Combine function outputs

of each section (S0, S1, S2, S3)

– Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations

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33

2210 xbxbxbby

Third-Order Polynomial

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343

232

3121

200

01233

01232

01231

01230

33

2210

3

128

163

443

41

33

Bn

b

Bn

b

BBn

b

BBn

b

SSSSB

SSSSB

SSSSB

SSSSB

xbxbxbby

First- and second-order Polynomial

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121

00

011

010

10

4

1

Bn

b

Bn

b

SSB

SSB

xbby

232

121

00

0122

021

0120

2210

2

272

98

1

2

26

Bn

b

Bn

b

Bn

b

SSSB

SSB

SSSB

xbxbby

First-order polynomial

Second-order polynomial

Adaptive Polynomial Fitting

• Fitting INL error from lower order polynomial to higher order

• Calculate RMS error of each polynomial

• Select the polynomial with least RMS error (when RMS error rising with higher order polynomial)

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Sigma-Delta Modulator

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S

1-bit DAC

intergrator

y(t)

quantiztion

x(t)

e(t)

Z-1 Y(z)X(z)

E(z)

1-bit first-order sigma-delta modulator

Transfer function in z-domain

Sigma-Delta Modulator (Cont.)

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First-order

Second-order

Third-order

17-bit ENOB104.1dB

Oversampling ratio (OSR)

Dithering DAC

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3

α=1

17bits

Resolution of dithering-DAC (bits)

Ov

ers

amp

ling

rat

io (

OS

R)

2

Simulation of DAC Test

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• 14-bit DAC• 16K ramp

codes• INL error up to

±1.5dB

Indices of 14-bit DAC-under-test

Simulation (Cont.)

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• Fitting results by different order polynomial

Indices of 14-bit DAC-under-test

Best-matching Polynomial

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Conclusion

• A built-in self-test and self-calibration solution for mixed-signal SoC is proposed

• A polynomial fitting algorithm is employed for INL error correction

• Fault-tolerance levels can be chosen for various applications

• Simulation results show significant improvement in linearity after calibration

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Q&A

Thank you!

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