Astronomical Array Control & Acquisition System

Astronomical Array Control & Acquisition System at NAOC Zhaowang Zhao Binxun Ye Research Labs for Astronomy National Astronomical Observatories, Chinese Academy of Science June 17 , 2005

SYTEM PERFORMANCE

1 Network based system. can be controlled remotely

2 Operate many kind CCD chips such as EEV, ATMEL, KODAK, SITE, FAIRCHILD, etc

3 Used the NIOS II family of embedded processors make the Camera has splendid features

4 Single chip FPGA Produces all of the signals and commands controlled by the master clock.

5 Logic and Analog circuits are synchronized completely and cuts off the noise dramatically.

Intelligent ControlUsing Nios II embedded processor for

designers accustomed to using stand-alone microprocessors and microcontrollers

10M/100M EtherNet Based Image AcquisitionAll of the control command through EtherNet. Voltage monitoring

12 bits ADC to measure all voltages.Temperature monitoringVery easy to upgrades and expand any control

command

System Performance

MULTI-READ OUT MODES

*Full Frame *Drift Scan by NEW IDEA *Frame Transfer *Binning *Windows

CCD Controller

shut terTEMPERATURE CONTROL

THUTTER

CCD

Dewar

VOLTAGE

PROTECTION

PREAMP

CCD BIAS

CCD CLK DRIVER

BIAS CONFIGURE

CCD CLK CONFIGURE

FPGA

NIOSEMBEDDED

PROCESSOR

HOSTCOMPUTER

16BITA/D

DCRSTORE

GAIN CDS

OPTOCOUPLER

POWER

Cryo Tiger Cooler

Cryo TigerCooler

CryoTiger Pump HOSTCOMPUTER

Dewar

CCD

WINDOW

CCD Support

Wi re

PRE-AMP

CCD CONTROLLER POWER

Cool inPipe

Cool ing Pipe

NET CABLE

EMBEDDED PROCESSOR CONTROL

FPGA

NIOSEMBEDDEDPROCESSOR

USER LOGIC

CCD Work MODE

GAIN CONTROL

BINNING FACTOR

Window ReadOut

Integrate Timing

CCD SEQUENCEV-CLOCKH-CLOCK

ETHER NET IRQ

MEMORY Interface

DMA INTERFACE

RS232 INTERFACE

PIO INTERFACE

USER INTERFACE

V CONFIGURE

SDRAM16MB

SRAM1MB

FLASH8MB

10M/100METHERNET

RJ45

EMBEDDED PROCESSOR STRUCTURE

NIOS PERFORMANCE• Nios Processor by Using Cyclone Device

EP1C20FC400 device • SRAM (1 Mbyte in two banks of 512 Kbytes,

16-bit wide) • SDR SDRAM (16 Mbytes, 32-bit wide) • Flash (8 Mbytes) • EPCS4 Serial Configuration Device (4 Mbits) 10/100 Ethernet physical layer/media access

control (PHY/MAC) • Ethernet connector (RJ-45) • Two serial connectors (RS-232 DB9 port)

ALTERA FPGA

• Cyclone family:• Work clock rates 250Mhz• EP1C20FC400 • Logic Elements: 20,060• Total RAM Bits: 294,912• Maximum user I/O pins: 301• Power supply 1.5V and 3.3V• Package: BGA 400

HARD WARE DESIGN

NIOS EMBEDDED PROCESSOR DESIGN

INSIDE STRUCTURE

CCD CONTROLLER OUTLINE

CCD CONTROLLER DURING TESTCCD CONTRLLER TEST

CryoTiger Cooler TEST

CCD Controller TEST

DEWAR

ALL of PCBs USED IN CCD VME –Similar BUS

VME –Similar BUS Features

• Standard VME BackBoard Can not Meet Astronomical Controller Requirements

• 6 Layer PCB

• 10 Kinds Power Supply Pins

with Large Current Line

• Separated Analog and Digital Ground plane

• Standard 96 Pin connector

• 6 Slots

NIOS INTERFACE BOARD

EMBEDDED PROCESSOR BOARD

NIOS PROCESSOR and INTERFACE BOARD

CCD ANALOG BOARD

CCD DRIVEN CLOCK BOARD

PRE-AMP BOARD

POWER SUPPLY BOARD

Control Software

• All Control Software written by Visual C++

• Operate system is WIN XP or WIN2000

START EXPOSURESTOP AND READ

STOP EXPOSURE

RESET CCD

EXPOSURE TIME SET

DRIFT SCAN FAXTOR

READ OUT MODE

BINNING FACTOR

WINDOW READ OUT COORDINATES

OVER SCAN SET

SHUTTER CONTRL

GAIN SELECTMASTER CLOCK SET

READ OUT SPEED

CCD SELECT

FILE NAME SETFILE PATH SET

MPP MODE SETTEMPERATURE MONITOR

MAIN CONTROL PROGRAM

INITIAL and ETHERNET SETUP

DRIVEN CLK SOFT SETUP

BIAS SOFT SETUP

Multi- CCDs Controlled by One Host

CCD CAMERA HEAD

…

…CONTROLLER

SWITCH

HOST

ETHERNET CABLE

ETHERNET CABLE

Test Result• Read out noise: 4ADU at 500K Speed

• Gain : 2.1 electrons/ADU

• Fill well : 270K electrons in MPP

• Linearity: 0.99997

• Transfer Efficiency: 0.999998 (Horizontal)

• Power supply: VCC, +5VA, ± 12V , ± 15V , ±30V

THANK YOU