ASIC_Design_Methodology.pdf

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ABSTRACT

Although ASIC design methodology has been used for more than

thirty years, today’s designers working with very deep ASIC

submicron technology face a new set of technical challenges.

These include leakage power, ming closure, signal integrity and

design for testability. To eciently address these issues, leading

EDA vendors incorporate advanced design and vericaon

techniques that help ASIC designers to improve the chance of rst-

me-right design success.

A recognized leader in providing ASIC design services, Infotech

leverages its proven, internal design ows and robust ecosystem

partnerships to produce 100% rst-pass silicon and on-schedule

delivery results. Backed by a 12 year record of more than 200 ASIC

tape-outs, Infotech also helps clients to develop new strategies for

product development and prepare detailed roadmaps for future

design trends.

Very Deep SubmicronASIC Design Methodology

A Whi te Paper

Introduction

This paper describes the Very Deep Submicron ASIC Design Methodology that is designed to produce 100% first-

pass silicon and on-schedule delivery results. It will discuss the critical issues that ASIC engineers face in design-

ing at very deep submicron nodes at 45nm and below, the ASIC design process, advanced techniques employed

in modern EDA to address these issues, and specific recommendations to improve the chance of first-time-right

design success for some of the design stages.

These recommendations are drawn from the experience of the Infotech design team in delivering more than 200

tape-outs and other ASIC design services over the past twelve years for the semiconductor industry.

Issues in Very Deep Submicron ASIC Technology

In recent years, market demand has increased for battery-operated devices with low power consumption as well

as for ASICs with higher frequency and functional density. These requirements have introduced new challenges for

design and test engineers, especially for very deep submicron nodes at 45nm and below. Reducing power supply

will lower the total power consumption, but it also increases the circuit sensitivity to noise since the transistor

threshold voltage is not scaling proportionally. Higher frequency and functional density increase the power con-

sumption but produce more heat in the design, resulting in larger power supply noise. Integration of several cores

for higher performance and throughput results in longer interconnects, thereby increasing coupling capacitance.

More specifically, the task of designing and verifying ASIC becomes significantly more complex due to the follow-

ing issues:

Leakage Power : ASICs are increasingly being used in consumer mobile devices where battery consumption is a

key differentiator among different products. As a result, IC designers face tremendous pressures to reduce power

consumption. In the very deep submicron nodes, leakage – the current consumed by the IC even when there is

no activity – significantly reduces the battery life for consumer mobile devices. To address this important issue, a

number of power reduction techniques have been invented especially for low-power semiconductor processes.

These techniques include:

Multi -threshold voltage: selectively using transistors with low switching thresholds (faster with higher leakage)

or high switching thresholds (slower with lower leakage) for individual logic gates

Multi -supply voltage: running selected functional blocks at different supply voltages

Power gating : shutting down the portions of the IC that are not being used

Clock tree optimization and clock gating : disabling portions of clock trees that are not being used at any partic-

ular time

Standby : gradually turning off clocks, PLLs and voltages during sleep mode, and turning them back on for op-

erational mode

Substrate biasing : biasing the body of the PMOS transistor to a voltage higher than Vdd, or to a voltage lower

than Vss in the NMOS transistor.

Operand isolation: reducing power dissipation in datapath blocks controlled by an ENABLE signal when

datapath is not active, preventing it from switching.

Figure 1: Leakage Power in Semiconductor CMOS Technology

Timing Closure: Exponential scaling in the past thirty years has made interconnect the main factor in determining

overall ASIC performance and reliability. Timing closure between synthesis and layout represents serious challeng-es to designers due to the significance of interconnect delays in the ASIC deep submicron technology. In addition,

the task is made even more difficult due to increased density of interconnect (which can consist of up to seven lay-

ers of closely-spaced metal), coupled with higher clock and edge rates that allow less time for signals to travel be-

tween cells. To address these issues, modern EDA tools analyze the interconnect effect throughout the design

process, especially in the early stages, by incorporating physical design throughout the entire ASIC design flow.

Signal Integrity (SI): Advances in interconnect technologies -- such as the increase in the number of metal layers,

stacked vias, and the reduced routing pitch -- have played a key role in the continuous improvement of integrated

circuit design and operating speed. However, interconnect parasitic reduces signal integrity due to propagation

delay, lateral coupling and crosstalk-induced delay. SI in the very deep submicron technology is worsened due to

the following reasons:

Lower supply voltage reduces noise margin

Smaller geometries induce coupling noise

Higher current density causes electromagnetic (EM) issues

Faster frequency worsens power/ground bouncing

Quick transient demands better transmission line design

Extreme performance requires inductance parasitic extraction

p-substrate

To improve ASIC performance integrity, reliability, and manufacturing yield, ASIC designers need to identify and fix

the causes that produce undesirable SI. Layout extraction to get the parasitics associated with the layout is often

used for this purpose. Usually the worst-case and the best-case parasitics are extracted and used in the simula-

tions to identify the cause of the noise and to determine the method for fixing it.

Design for Testability (DFT): Due to the enormous number of transistor count and functions, complex testing

needs to be performed for very deep submicron ASICs to ensure that the product hardware contains no defects

that could adversely affect the correct functioning of the product. DFT techniques can be used to add certain test-

ability features to an IC hardware product design. These added features are designed to easily develop and apply

manufacturing tests for the designed hardware.

In recent years, power -aware DFT has been a topic that has caught a great deal of attention from the ASIC and

EDA industries due to the need for managing the chip power. Scan-chain test architecture can be made power

aware by building the test architecture that mirrors the low-power functional architecture of the design. The tech-

niques used in DFT will be discussed in a later section of this paper.

ASIC Design Methodology

ASIC Design Methodology is not new and has been around for more than thirty years. However, very deep submi-

cron nodes require advanced techniques in the ASIC design process - techniques which were not introduced until

recently. Before exploring these new techniques, let’s review the ASIC design process that is shown in Figure 2.

The ASIC design process begins with writing a functional description that contains detailed requirements for the

chip. The first step is similar to FPGA design. The following tasks are run in parallel:

Writing a synthesizable register transfer level (RTL) description, either in Verilog or VHDL, of the device

Writing a behavioral model which is used to verify that the design meets its requirements

Writing a verification plan and a corresponding verification environment which describes and implements the

method of proving the design correctness

To reduce the probability of design error, the RTL description is verified against the behavioral model. The RTL

description is usually first converted to a gate-level description of the circuit by a logic-synthesis tool. The tool

reads RTL input, user -specified constraints and a cell library from the foundry. The output of the synthesis process

is a gate-level netlist.

Most modern ASIC designs are so complex that DFT techniques during the design stages are required to distin-

guish valid from faulty chips at the production stage. DFT techniques include:

Scan insertion - a methodology for linking all registers into one long shift register (scan path). This can be used

to check the small parts of a design instead of the entire design (the latter being almost always impossible).

Memory built -in self test (MBIST)

-a device used to check ASIC embedded memories. After being triggered, it

feeds specific test patterns to the memory module, reads back and compares results.

Automatic test pattern generation (ATPG) - a method of creating test vectors for scan paths and MBIST auto-

matically. Most modern EDA tool chains incorporate such a feature.

After the DFT insertion, the gate-level netlist must undergo formal verification to prove that the RTL and netlist are

equivalent.

Figure 2: The ASIC Design Flow

Architectural Design

RTL Design Behavioral Modeling

RTL Verification

Logic Synthesis

DFT Insertion

Formal Verification

Post-SynthesisTiming Analysis

Floor -Planning andPlacement

Routing

Post-Layout Timing Analysis

DRC and LVS

Tape-out

Analysis is made on the preliminary timing results after synthesis, and critical paths are checked against the pro-

ject performance requirements. If needed, the RTL description, constraints or synthesis options are modified, and

the synthesis is repeated. When timing constraints are finally met, the synthesis results are then used by place-

ment and routing tools to create a physical layout.

The layout process consists of floorplanning, placement and routing . Some other important tasks are performed at

this step, including clock tree insertion. The quality of early design deliverables such as chip specification, RTL

code, IP blocks and the functional verification plan have a tremendous impact on the efficiency of an ASIC physical

implementation phase.

Final (post-layout) timing results are again compared with performance requirements. If it doesn't fit, the floorplan

can be changed or the placement can be run with other parameters.

The last stage before the tapeout (a transition point from the ASIC design stage to the ASIC manufacturing stage)

includes the following checks:

Design rule check (DRC), a check to make sure that the layout conforms to the foundry-specific rules

Layout versus schematic (LVS), a formal equivalence check between the post-synthesis netlist and the final

layout

Finally, the resulting layout in GDSII format is handed to the designated semiconductor foundry to start the ASIC

manufacturing process.

Design and Verification Techniques for the ASIC Very Deep Submicron Technology

To address the very deep submicron technology issues, many leading EDA tools incorporate several advanced

design and verification techniques such as the following:

RTL Design

The very deep sub-micron ASICs are characterized by higher density and higher performance in the smaller form-

factors. ASIC designers are faced with significant challenges in accurately modeling the circuit RTL behaviors,

including:

Accurate modeling of transistor switching, power consumption and relationship between a gate and the associ-

ated interconnect.

Second-order effects such as impact ionization, drain-induced barrier lowering, and channel-length modulation.

Performance variance for transistors fabricated with different-sized geometries (up to 60%). It is important to

note that the transistor drain-to-source current can vary greatly, resulting in low predictability for switching time

and power dissipation.

Incompatibility in scaling between the wire geometries and the transistor geometries.

Smaller operating voltages that cause an increase in the transistor input slope, output load and temperature

sensitivities. Because of this, transistors must operate with a smaller transition region.

To resolve these issues, modern EDA tools employ the following modeling and characterization techniques:

Power model characterization that enables dynamic or static gate-level power consumption analysis by char-

acterizing the actual current drawn from the power grid at any given time for individual cells

Modeling voltage impact on delay for low-power applications

Modeling effects of noise introduced by coupling capacitances in the complex scenarios where multi

thresholdvoltage and multi-voltage devices commingle

Current -based modeling method that models current versus time and multi-piece capacitances to enable more

accurate static timing analysis (STA)

Statistical leakage power modeling

Statistical process variation modeling

Verification

The ASIC design verification planning is critical for supporting optimal time-to-market. At the same time, it is chal-

lenging because of its multi-disciplinary nature that involves design and verification engineers at different levels of

abstraction and complexity. Performing full verification of an ASIC design is time-consuming and quite possibly not

even efficient since most of the building blocks are verified in the stand-alone environment. However, there are too

many points of failure in a complex ASIC to have it signed-off without extensive verification.

To ensure high efficiency on the verification effort, verification should not re-perform all block level simulations. In-

stead, verification must focus on the chip-level integration features and the interaction among various blocks in the

design. This ASIC is then verified in a piece-wise manner, leveraging on the verification effort that is done at the

block level. For this approach, the inter -block interfaces and other integration design become the critical points for

verification. For assertion and functional coverage, the use of SystemVerilog (an IEEE-standard, high-level verifi-

cation language) helps to assert these critical points and at the same time collect coverage to ensure that all of

these points are exercised.

The advanced functional verification techniques used for the very deep submicron ASIC nodes contain the follow-

ing characteristics:

Constrained random testing (CRT)

Transaction-level stimulus modeling: High-level data structures (objects) encapsulate stimulus (akin to

conventional test vectors) into transactions (high-level functionality such as read, retry, drop packet,

etc.) The test bench generates and processes these high-level transactions to increase efficiency com-

pared to writing test vectors manually.

Random stimulus generation: Constraints describe the legal range and relationship among transactions

(for example, a write operation that must have addresses between 10 and 100). Solving these con-

straints at runtime provides pseudo-random stimulus generation.

On-the

-fly response checking : The test bench contains a reference model of the design under test

(DUT) and can therefore predict the response of the DUT. Design failures are determined at runtime.

Coverage driven: Functional coverage models describe all the features that need to be verified. As ran-

dom tests are run, the coverage models provide a metric that can be used to track verification progress.

Assertion-based verification

Assertion-based checkers/monitors: As defined by the test plan, assertion based monitors are deployed

at the block and chip boundaries to capture intended behavior. Additionally, micro-architecture level as-

sertions are used to define the designer’s assumptions that might not be part of the test plan.

Assertion-based coverage: Assertions are used to ensure that the stimulus can exercise gray-box condi-

tions within the RTL. Coverage of these assertions provides a measurement of gray-box testing.

A successful implementation of constrained-random verification requires an understanding of several key success

factors, including:

Team expertise: The team should include at least one engineer with a strong background in object -oriented

programming (OOP). This background will help in using the OOP semantics of a high-level verification lan-

guage to architect test bench components for reuse and scalability.

High-level verification language and methodology : The high-level verification language SystemVerilog provides

a range of constructs that simplify the task of implementing high level software-like algorithms. Leading EDA

tools also include methodologies that capture best practices and recommendations for developing a more effi-

cient verification environment to increase the likelihood of first-pass silicon success.

Verification IP (VIP): A high-quality, proven VIP can significantly increase the productivity of the verification

team by reducing the test bench development time.

Regression environment should contain the following characteristics:

Support for executing a single test with multiple random seeds to create multiple test cases.

Ability to gather and merge functional-coverage metrics to generate reports for measuring verification

progress and completeness, in addition to traceability from coverage to test case.

Ability to reproduce a failing random simulation for debugging purposes.

Adequate disk space and memory for compiling and running the simulations.

Very deep-submicron technology poses new challenges to ASIC testing. In particular, crosstalk and transient faults

are difficult to detect with traditional methods. The scan-based delay fault test has gained popularity in the industry

over the past several years as a reliable method for post-silicon performance verification. At first, the industry used

functional patterns, but as the design size became larger, the high cost of generation (due to the manual genera-

tion of patterns) and low fault coverage forced functional -at -speed test as a supplement to structural test in many

semiconductor companies' DFT flow. Not surprisingly, scan-based delay fault test methods gained attention pri-

marily due to their very high fault coverage and their simple procedure to generate patterns.

In a scan-based delay fault test, several slow clock cycles are inserted before the fast clock is applied for detecting

delay faults. As a result, considerable illegal states can be avoided, and IR drop can be reduced. These illegal

states are not necessarily computed before test generation. They can be accumulated and expanded during the

automatic test pattern generation (ATPG) process. The derived illegal states are then used to guide test generation

for the remaining faults. In addition, high-performance designs at a nanometer scale must be tested at functional

clock speeds to ensure correct field operation. This continues to be a growing challenge, especially due to the in-

creased presence of these effects. The transition delay fault testing has been widely used to ensure that fabricat-

ed chips meet the designed timing specifications and to detect any timing-related failures.

In this testing method, ATPGs deterministically target a transition fault, then either perform random filling to in-

crease the fortuitous detection of unmodeled faults or use compression algorithms to reduce the total pattern

count. The scan-based path delay fault test and the transition delay fault test, taken together, can provide a high

quality test for the very deep submicron ASICs.

The following recommendations can help improve the chance of success in DFT:

JTAG: This is the IEEE 1149.1 standard for test insertion techniques. According to this standard, the compliant

ASIC contains Test Access Ports (TAP) to access the IC, shift registers, data registers and boundary scan cells,

and a state machine (TAP controller) to execute the JTAG instruction. Figure 3 shows the JTAG implementation

according to the IEEE specification. The following items describe the IO functions used in JTAG test insertion:

TDI = Serial Test Data Input signal that sends the data into the chip. After entering the ASIC, the data will be

stored in the instruction register or in one of the data registers

TDO = Serial Test Data Output signal

TCK = Test Clock signal that drives the boundary scan logic

TMS = Test Mode Select signal that drives the state of the TAP Controller

nTRST = Test Reset signal that serves as an optional reset

Figure 3: The JTAG Implementation

It is a recommended practice to have pull-up IO pads for nTRST, TDI and TMS signals since they must have pull-

up resistors (according to IEEE 1149.1). All IO pad functional signals should be driven to and from the core mod-

ule. IO modules should not include standard cells, TIEHIGH and TIELOW cells. During the logic synthesis stage,

the “set don’t touch” attribute should be applied to the IO module to avoid the insertion of standard cells.

Scan Insertion: Scan tests cover stuck -at

-faults caused by manufacturing issues. It is achieved by replacing all

flip-flops in the design with the chained scan-type flip-flops which enable designers to control and observe the cir-

cuit test results. To increase the testing efficiency, ASIC test engineers need to consider some factors for scan in-

sertion such as the number of flip-flops, number of clock domains and clocking strategy, scan-chain length limita-

tion, TAP controller to control the scan, FastScan models and Verilog/VHDL models for the standard cells, IOs and

IPs, automated test equipment (ATE) used for testing and its pin and speed configuration.

In general, when inserting scan-chain, ASIC test engineers should avoid the following scenarios that can produce

an adverse effect on the testing effort:

Combination of POSEDGE and NEGEDGE flip-flops

Tristate elements

Latches

Combinational feedbacks

Redundant logic

Internally generated clocks

ASYNC SET/RESET signals

Output of the PLL (if PLL is used in the design)

Each scan-chain should have an input pin and an output pin. It is also recommended that at least one if not two

extra pins are allocated for SCANMODE and SCANENABLE (signals which control the scan test). To improve test

coverage, all macros should have wrappers. These wrappers contain the insertion of the registers and muxes

which are used to bypass macro inputs and outputs.

MBIST: This is used for testing IC embedded memories. Before implementing MBIST, ASIC test engineers needto consider several factors: memory types and sizes, number of memories, latencies during R/W cycles, clock do-

main used for each memory in the circuit, whether MBIST will be implemented at RTL or gate-level netlist, whether

MBIST operates with Bypass Clock or PLL Clock or both.

It is a recommended practice to implement MBIST in Bypass Mode using an external clock. All the clock-gating

logic should be bypassed by a control signal during BIST mode. The BIST controller logic should stay close to the

memories to avoid congestion. Controller grouping is optimal if memories are grouped based on factors such as

clock domain, memories size, or memories location. To improve ATPG coverage, Bypass registers should be in-

cluded in the BIST Collars.

Power -Aware DFT: As mentioned before, power management is a major issue in designing very deep submicron

ASICs. In power -aware DFT, scan chain test architecture can be made power -aware by building the test architec-

ture that mirrors the low-power functional architecture of the design. The power -aware DFT architecture typically

has two major elements:

aware scan chain design and test modes: Equal numbers of scan segments are inserted in all logicsubsets operating at different power domains. Chip-level scan chains are formed by placing one or more of

these scan segments from each switchable hierarchy to build test modes that correspond to all the power

modes of the design.

Power test access mechanism (PTAM): Modern EDA tools have an automatic process to generate and insert a

PTAM into the existing power controller of the design. This simple structure enables control of power switches

during test and enables selection and stabilization of desired power modes during test.

To help ASIC designers adopt advanced power reduction techniques such as power -aware DFT, the Silicon Inte-

gration Initiative (Si2) creates Common Power Format (CPF). CPF is a format for specifying power -saving tech-

niques early in the design process, enabling them to share and reuse low-power intelligence. It is very widely

used in the low-power design and verification process for the very deep submicron ASICs.

Timing Closure

For very deep submicron technology, IR Drop is a one of the major issues in timing closure. It affects both timing

and functionality, and it can have a significant impact on transistor performance. Some IR Drop issues include:

Leff and W variation

IR Drop variation

Interconnect variation

Figure 4: TimingClosure Operations

Figure 4 shows the

operations used in the

ASIC design flow to

catch circuit IR Drop

problems. Most

leading EDA tools

today have IR Drop

analysis as part of

their offering.

Infotech ASIC Design Services

Infotech Enterprises is a leading dedicated global engineering solutions company, headquartered in Hyderabad,

India. Our HiTech business unit provides a number of ASIC design services for semiconductor companies, rang-

ing from RTL to GDSII. We support a design partnership approach developed for 100% first-pass silicon tape-out

results, regardless of which stage in the ASIC design flow that we start working with the customer. Figure 5 shows

an abbreviation of the ASIC design flow, and the corresponding services and ownerships shared between Infotech

and the customer throughout each stage of the flow.

Using a robust, internal design flow combined with the ability to handle complex ASIC functional verification,

Infotech has so far delivered sixty ASICs with over 5 million gates and twelve ASICs with over 10 million gates.

Our team has deep experience in working on all technology nodes, from 180nm down to 28nm. We work closely

with the semiconductor foundry, EDA and IP partners in our ecosystem to provide a seamless ASIC design envi-

ronment, from RTL to GDSII, for all our semiconductor customers. Figure 6 shows our ecosystem partnershipsand Figure 7 shows successful engagements that Infotech has delivered over the past several years.

Figure 5: Infotech ASIC Design Services and Ownerships

Figure 6: Infotech ASIC Ecosystem Partnerships

Figure 7: Examples of Successful Infotech Engagements

TSMC Design Center Alliance (DCA) Partner

GLOBALFOUNDRIES Design Partner

Common Platform Design Enablement Partner

Cadence Verification Alliance Partner

IP Vendor Relationship - ARM, Virage/Synopsys

Altera Consultants Alliance Partner (ACAP)

EDA Partners - Cadence, Synopsys, Mentor Graphics

Member - Global Semiconductor Alliance

About the Author

Ms. Tina Tran has 20 years of semiconductor industry experience. She started her career as an ASIC design engi-

neer, and then later moved to application engineering, technical marketing and product marketing job functions, all

within LSI Logic Corporation. She also developed a market understanding of Digital Video and Multimedia applica-

tions while working for C-Cube Microsystems in a product line management role. While at Altera Corporation, a

premier FPGA manufacturer, she helped the company to successfully market their products into the high-volume

Digital Television and Consumer Electronics market for the first time. Ms. Tran holds a Bachelor of Science de-

gree in Electrical Engineering from Texas A&M University, and a Master of Business Administration degree from

Santa Clara University.

References Nisar Ahmed, “High Quality Delay Tests for Very Deep Submicron Designs”, Dissertations Collection for University of Connecticut.

Jeremy Lee and Mohammad Tehranipoor, “LS-TDF: Low -Switching Transition Delay Fault Pattern Generation”,University of Connecticut.

Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, and Kijian Shi, “Low Power Methodology Manual for System-on-Chip Design”, Synopsys, Inc. and ARM, Limited.

Srikanth Jadcherla, Janick Bergeron, Yoshio Inoue, and David Flynn, “Verification Methodology Manual for Low Power”, Synopsys, Inc., ARM Limited, and Renesas Technology Corp.

Satheesh Kumar Sompalle and Madhu Kiran TV., “Challenges In Timing Closure In Deep Submicron Technolo-gies”, NXP Semiconductors.

Jordan Lai, “The Design Challenge for the Very Deep Submicron Technology”, TSMC Corp.

Jason Cong, “Timing Closure Based on Physical Hierarchy”, University of California, Los Angeles.

Steve Schulz, “Deep-Submicron Timing Closure”, Texas Instruments, Inc.

Narayana Kodeti, “Design for Testability Guidelines”, Infotech-Enterprises, Ltd.

Alberto Sangiovanni -Vincentelli and Chi -Ping Hsu, “A Practical Guide to Low -Power Design”, Cadence DesignSystems.

Daniel Blong, “What If What If Analysis Won’t Work at 28nm?”, Magma Design Automation.

Thia Chin Tong, Cheow Wai Meng, and Tan Lay Hong, “ARM -based SoC Verification with SystemVerilog Functional Coverage”, Solomon Systech, Pte. Ltd.

Kwamina Ewusie and Rajat Mohan, “Managing Functional Verification Projects”, Synopsys, Inc.

About Infotech Enterprises

Infotech Enterprises provides leading-edge engineering

solutions, including product development and lifecycle

support, process, network and content engineering to

major organizations worldwide. With nearly two decades

of continuous growth, Infotech leverages a "Global

Delivery and Collaborative Engineering Model" to achieve

measurable and substantial benefits for our clients.

Whether your organization needs to design innovative

products faster, optimize R&D costs, increase market

share, enhance operational efficiency or maximize the

return on investment in your networks, Infotech Enterpris-

es is the ideal partner.

With Global Headquarters in Hyderabad, India, Infotech

employs over 8,000 engineers across 30 global locations.

We adopt a proactive approach to serve our clients with

our best-in-class delivery centers in North America, Eu-

rope, Middle East and Asia Pacific. Our clients span mul-

tiple industries such as Aerospace, Consumer, Energy,Medical, Heavy Equipment, Rail, Semiconductor, Telecom

and Utilities and include 22 'Fortune 500' and 27 'Global

500' blue chip organizations.

In order to consistently create and deliver services that

exceed clients' expectations and enhance their business

agility, Infotech employs a framework of robust internal

processes to ensure IP Security, quality-of -solution and on

-time delivery. Our quality management framework is

compliant to global standards which include: ISO 9001,

ISO 27001, TL 9000, AS9100B, ISO 13485 and CMMi

Level 5.

Contact us today to learn more about how our global

engineering services can help transform your innovation

risk into steady and secure marketplace advantage.

engineering@infotech-enterprises.com

www.infotech-enterprises.com

Copyright 2011, Infotech Enterprises. All rights reserved. Without prior written consent from Infotech Enterprises, no part of this document mayreproduced, stored in a retrieval system, transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or any

her communication media. The information contained herein is subject to change without notice. Trademarks mentioned, if any, are the propertytheir respective owners.

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ASIC_Design_Methodology.pdf

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