Anthony J. YuGuy G.F. Lemieux August 25, 2005

Defect-tolerantDefect-tolerant FPGA FPGASwitch Block and Connection Block Switch Block and Connection Block

with with Fine-grain RedundancyFine-grain Redundancy for for Yield EnhancementYield Enhancement

Anthony J. YuAnthony J. Yu Guy G.F. LemieuxGuy G.F. Lemieux

August 25, 2005August 25, 2005

FPL'05 - PresentationFPL'05 - Presentation 22

OutlineOutline

Introduction and MotivationIntroduction and MotivationPrevious ApproachesPrevious ApproachesFine-grain RedundancyFine-grain RedundancyResultsResultsConclusionsConclusions

Introduction and MotivationIntroduction and MotivationScaling introduces Scaling introduces new typesnew types of defectsof defectsSmaller feature sizes Smaller feature sizes susceptible to susceptible to smaller defectssmaller defectsExpected resultsExpected results– Defects per chip increasesDefects per chip increases– Chip yield declinesChip yield declines

FPGAs are mostly FPGAs are mostly interconnectinterconnect

FPGAs must tolerate FPGAs must tolerate multiple multiple interconnect defectsinterconnect defects to to improve yield (and $$$)improve yield (and $$$)

General Defect Tolerant General Defect Tolerant TechniquesTechniques

Defect-tolerant techniques minimize impact Defect-tolerant techniques minimize impact (cost) of manufacturing defects(cost) of manufacturing defects

FPGA defect-tolerance can be loosely FPGA defect-tolerance can be loosely categorized into three classes:categorized into three classes:– Software Redundancy – use CAD tools to map Software Redundancy – use CAD tools to map

around the defectsaround the defects– Hardware Redundancy – incorporate spare resources Hardware Redundancy – incorporate spare resources

to assist in defect correction (eg. Spare row/column)to assist in defect correction (eg. Spare row/column)– Run-time Redundancy – protection against transient Run-time Redundancy – protection against transient

faults such as SEUs (eg. TMR)faults such as SEUs (eg. TMR)

Previous work – 1 – XilinxPrevious work – 1 – XilinxXilinx’s Defect-Tolerant ApproachXilinx’s Defect-Tolerant Approach– Customer (knowingly) purchases “less that perfect” partsCustomer (knowingly) purchases “less that perfect” parts

Customer gives Xilinx configuration bitstreamCustomer gives Xilinx configuration bitstreamXilinx tests FPGA devices against bitstreamXilinx tests FPGA devices against bitstream– Sells FPGA parts that “appear” perfectSells FPGA parts that “appear” perfect– Defects avoid the bitstreamDefects avoid the bitstream

Limitation:Limitation:– Chips work only with given bitstream – no changes!Chips work only with given bitstream – no changes!

Previous work – 2 – AlteraPrevious work – 2 – AlteraAltera’s Defect-Tolerant ApproachAltera’s Defect-Tolerant Approach– Customer purchases “seemingly perfect” partsCustomer purchases “seemingly perfect” parts

Make defective resources inaccessible to userMake defective resources inaccessible to userCoarse-grain architectureCoarse-grain architecture– Spare row and column in array (like memories)Spare row and column in array (like memories)Defective row/column must be bypassedDefective row/column must be bypassed– Use the spare row/column insteadUse the spare row/column instead

Limitation:Limitation:– Does not scale well (multiple defects)Does not scale well (multiple defects)

ObjectiveObjectiveProblemProblem– FPGA yield is on decline because of aggressive FPGA yield is on decline because of aggressive

technology scalingtechnology scaling

Proposed SolutionProposed Solution– Defect-tolerance through redundancyDefect-tolerance through redundancy

Important ObjectivesImportant Objectives– Interconnect defects important (dominates area)Interconnect defects important (dominates area)– Tolerate multiple defects (future trend)Tolerate multiple defects (future trend)– Preserve timing (no timing re-verification)Preserve timing (no timing re-verification)– Fast correction time (production use)Fast correction time (production use)

Our Proposed SolutionOur Proposed SolutionFine-grain Redundancy (FGR) – Fine-grain Redundancy (FGR) –

Defect Avoidance by ShiftingDefect Avoidance by ShiftingDefectSpare

a) Original b) Corrected

+1 -1-1

Island-style FPGAIsland-style FPGA

Directional Switch BlockDirectional Switch Block

Defect-tolerant Switch BlockDefect-tolerant Switch Block

-1 0-2

+1 0+2

-1 0-2

+1 0+2

a) Original b) Defect-tolerant

HSPICE SchematicHSPICE Schematic

16:1MUX

3:1MUX

4:1MUX

omuximux

Bypass pathDirectionalmultiplexer

Switch Implementation OptionsSwitch Implementation Options• Several detailed implementations are possible• Trade off area / delay / yield(repairability)

Defect Avoidance –Defect Avoidance –Switch Implementation Switch Implementation Option 1Option 1

Can avoid contention by pre-shifting the red signal… OR…

[ lower area overhead, lower yield improvement ]

Defect Avoidance –Defect Avoidance –Switch Implementation Switch Implementation Option 2Option 2…OR … can avoid contention by embedding the IMUX

[ higher area overhead, best yield ]

ResultsResults

AreaAreaDelayDelayArea Delay ProductArea Delay ProductYieldYieldSummarySummary

Area ResultsArea Results

Delay ResultsDelay Results

Area-Delay ProductArea-Delay Product

Yield – 1Yield – 1Switch Implementation Affects Yield Switch Implementation Affects Yield

* Assumes all bridging defects

Yield – 2Yield – 2Larger Arrays Tolerate Larger Arrays Tolerate MoreMore Defects Defects

SummarySummary

ConclusionsConclusionsFGR meets desired objectivesFGR meets desired objectives– Tolerates Tolerates multiplemultiple randomly distributed defects randomly distributed defects– Defect correction Defect correction does not perturb timingdoes not perturb timing– Tolerates an Tolerates an increasing numberincreasing number of defects as array size of defects as array size

increasesincreases– Correction can be applied Correction can be applied quicklyquickly

FGR has different implementation optionsFGR has different implementation options– Trade-offs between yield, area and delay can be madeTrade-offs between yield, area and delay can be made– Best Area: EN11Best Area: EN11– Best Delay: EM11Best Delay: EM11– Best Yield: EM22Best Yield: EM22

Thank you!Thank you!

anthonyy@ece.ubc.caanthonyy@ece.ubc.ca

Single-length DefectsSingle-length Defects

EnhancedSwitch Block

Equivalent Faults

Wire Driver

Double-length DefectsDouble-length Defects

Equivalent Faults

Minimum Fault-free Radius (MFFR)Minimum Fault-free Radius (MFFR)

Anthony J. YuGuy G.F. Lemieux August 25, 2005

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