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Analog Integrated Circuits
Hossein Shamsi
1
Why Analog?
• Processing of Natural Signals
2
Why Analog?
• Digital Communication
3
Why Analog?
• Disk Drive Electronics
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Why Analog?
• Wireless Receivers
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Why Analog?
• Optical Receivers
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Why Analog?
• Sensors
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Why Analog?• Microprocessors
– Distribution and timing of data and clocks
– Non-idealities in signal and power interconnects
– Issues related to the package parasitics.
• Memories– They needs high-speed “sense amplifiers”
“High-speed digital design is in fact analog design.”8
Why Integrated?• The birthday of Electronics is 1900.
• The main building block vacuum tube• Drawbacks
• Large size• Small life-time
• The birthday of Microelectronics is 1960 (25μm Technology).• Microelectronics: the knowledge of integration of transistors in a small area.• The main building block Transistor• Advantages
• small size• Infinite life-time
• Moore’s law: the number of transistors per chip has continued to double approximately every 1.5 years.
• 25μm CMOS Technology 45nm CMOS Technology • CPU (3cm×3cm) 100-million transistors• Handset 1-million transistors• Memory 1-billion transistors
• The state-of-the-art microelectronics products:• Laptop• Cell phone• Digital camera
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Why CMOS?• Advantages:
• CMOS technology is a low-power technology.• In order to realize digital circuits in CMOS technology, we need fewer devices than its
Bipolar or GaAs counterparts.• Disadvantages
• Slower• Noisier
• Therefore CMOS technology is a helpful technology for digital circuits.• Since we want to integrate both the analog and digital circuits on a same
substrate, so we must design the analog circuits in CMOS technology.
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Structure of a NMOS transistor
Ddrawneff LLL 2−=
Typical values:
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N-Well Process
12
MOS Symbols
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MOS I/V Characteristics
Formation of the depletion region
Formation of the inversion layer
12 GG VV >
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MOS I/V Characteristics
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Derivation of I/V Characteristics
A semiconductor bar carrying a current I
Snapshots of the carriers one second apart.
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Derivation of I/V Characteristics
( )THGSoxd VVWCQ −−=
( )[ ]THChGoxd VxVWCQ −−= −( )[ ]THchGoxd VxVVWCQ −−−=
( )[ ]vVxVVWCI THGSoxD −−−=17
Derivation of I/V Characteristics
Since ID is constant along the channel
( )[ ]vVxVVWCI THGSoxD −−−=
18
voltageeffectivevoltageoverdriveVV THGS ≡≡−
ratioaspectL
W≡
regiontriodeVVVVVVVif THGSDSTHGDTHGS →−<≡>> ,19
( ) regiontriodedeepVVVif THGSDS →−<< 2
So we have:
Linear operation in deep triode region
MOSFET as a controlled linear resistor20
Saturation of the Drain Current
Pinch-off Behavior21
Saturation of the Drain Current
( )[ ]∫∫−
=
′
=
−−=THVGSV
VTHGSnOX
L
xD dVVxVVWCdxI
00
µ
22
Saturation Region
For long channel transistor, we have: LL ′≅
So the above formula is simplified as follows:
( )2
21
THGSoxnD VVL
WCI −= µ23
Transconductance of MOSFET
( )2
21
THGSoxnD VVL
WCI −= µ
24
Conceptual Visualization of Saturation and Triode Regions
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Second Order Effects•Body Effect•Channel-Length Modulation•Subthreshold conduction•Leakage current•Short-channel effects
If VSB>0 the threshold voltage VTH is increased as follows:
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Second Order Effects•Body Effect•Channel-Length Modulation•Subthreshold conduction•Leakage current•Short-channel effects
The actual length of the inverted channel gradually decreases as the value of VD increases. In other words, L‘ is in fact a function of VDS
(from semiconductor devices course)
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Second Order Effects
Therefore, for longer channels, λ is smaller.
Channel-length modulation results in a nonzero slop in the ID /VDScharacteristic.
L1
∝λDSVLL λ=∆
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Second Order Effects
In reality, for VGS<VTH a weak inversion layer still exist and some current flows from D to S. This phenomena is called weak inversion or subthreshold conductance.
•Body Effect•Channel-Length Modulation•Subthreshold conduction•Leakage current•Short-channel effects
5.1,75 =≥ nmVVDS
(David Johns)
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Second Order Effects
The Leakage current of the PN junctions is important in estimating the maximum time a sample-and-hold circuit or a dynamic memory cell can be left in hold mode.The leakage current doubles for every 11 °C rise in temperature.
•Body Effect•Channel-Length Modulation•Subthreshold conduction•Leakage current•Short-channel effects
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Second Order Effects
This phenomena will be discussed later (chapter 17, Razavi).
•Body Effect•Channel-Length Modulation•Subthreshold conduction•Leakage current•Short-channel effects
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MOS Device Layout
The two most important masks are:•Active region mask•Gate polysilicon mask
The intersection of these two masks becomes the channel region of the MOS transistor.
The design rules for laying out transistors are often expressed in terms of λ where λ is ½ the gate length.
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MOS Device Layout
When we are drawing the layout of a circuit, we must perform both the DRC and LVS tests.DRC Design Rule CheckLVS Layout Versus Schematic 33
MOS Device Layout
Example:
Area:
Peripheral: WλPs 210 +=
WλAJ ×= 51
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Integrated Resistors
35
Types of integrated capacitors
36
Integrated capacitors
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Capacitors Features
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MOS Device Capacitances
C1 or Cch: oxide capacitanceC2 or Cd: depletion capacitanceC3,C4: overlap capacitanceC5,C6: junction capacitance
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Effect of Layout on Parasitic Capacitances
( ) ( ) jswjSBDB CEWCEWCC ++×== 2
40
MOS Device Capacitances(Saturation Region)
MOS Device Capacitances(Saturation Region)
oxovoxeffGS WLCWCCWLC32
32
≅+=
oxDovGD CWLWCC ≅=
0≅GBC CGB is neglected because inversion layer act as a shield.
( )
perimetersourcePareasourceA
voltageinbuiltmV
CC
V
CC
WLACPCAAC
ss
Bm
B
SB
jswjswm
B
SB
jj
effchjswsjchsSB
::
:,4.03.0
1
,
1
,
00 −≤≤
+
=
+
=
=++=
− ϕ
ϕϕ
m
B
DB
jswjswm
B
DB
jjjswdjdDB
V
CC
V
CCCPCAC
+
=
+
=+= −
ϕϕ1
,
1
, 00
42
MOS Device Capacitances(Deep Triode Region)
MOS Device Capacitances(Deep Triode Region)
ovox
GS WCWLCC +≅2
0≅GBC CGB is neglected because inversion layer act as a shield.
m
B
SB
jswjswm
B
SB
jjjswsj
chsSB
V
CC
V
CCCPCAAC
+
=
+
=+
+= −
ϕϕ1
,
1
,2
00
m
B
DB
jswjswm
B
DB
jjjswdj
chdDB
V
CC
V
CCCPCAAC
+
=
+
=+
+= −
ϕϕ1
,
1
,2
00
ovox
GD WCWLCC +≅2
44
MOS Device Capacitances(Cut-off)
ovGS WCC =
( )( ) oxGBGd
oxd
oxdGB WLCCVC
WLCCWLCCC ≅⇒<<+
≅ 0ife,capacitancdepletion:,
m
B
SB
jjjswsjsSB
V
CCCPCAC
+
=+=
ϕ1
, 0
m
B
DB
jjjswdjdDB
V
CCCPCAC
+
=+=
ϕ1
, 0
ovGD WCC =
45
Beahvior of MOS Device as a Capacitor
NMOS operating in accumulation region
46
MOS Low-Frequency Small-Signal Model(active region)
47
MOS Small-Signal Model(active region)
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MOS Small-Signal Model(triode region)
( )THGSoxn
ds
VVL
WCr
−=µ
1
49
MOS Small-Signal Model(Turn off region)
50
MOS SPICE Model
TechnologyCMOSμm0.5
51
MOS SPICE Model
52
Comparison between NMOS and PMOS
PMOS devices are quite inferior to NMOS transistors.
For example, due to the lower mobility of holes: oxnoxp CC µµ 5.0≅
nmpm gg <
Besides, for a given current and dimension we have:nopo rr <
53
FinFET
• FinFET utilizes a three-dimensional structure, which results in small channel length about 20nm.
• Equivalent channel width: • Typically, WF=6nm, HF=50nm.• In practice, the designer does not have any control on WF and HF.• Wider transistors can be obtained by increasing the number of fins.
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Utilizing Multiple Fins
Top View
55
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