An FPGA based Phased Array Processor for the Sub ...jweintro/vlbi/forbob/Vinayaks Graphics... · An...

An FPGA based Phased ArrayProcessor for the Sub Millimeter

ArrayVinayak Nagpal

Chalmers University of Technology, Sweden

advised by

Jonathan Weintroub

Smithsonian Astrophysical Observatory

Vinayak Nagpal, CTH – p. 1/28

Outline

Introduction: What we plan to build and why?

Outline

Infrastructure: What did we have in hand?

Outline

Design: How we went around building it?

Outline

Results: Does it work?

Outline

Future: Where to go from here?

Outline

Future: Where to go from here?

Demonstration in M247 for those who want tosee it work and discuss in more detail.

Motivation

(VLBI) at 0.8 mm with sufficiently long baselines →

≈ 20 µas resolution.

In sub millimeter electron scattering is reduced.

Imaging observation of the event horizon in a blackhole e.g. SgrA∗, M87.

Sub-millimeter telescopes: JCMT, CSO, HHT, (ALMA)etc and SMA.

SMA full collecting area + JCMT + CSO → we need aphased array with interface to standard VLBIrecorders, i.e. Mark V.

Project Objectives

Proof of Concept

Development time → 10 months.

INPUT: 8 Antennas (SMA or JCMT/CSO),Single Polarization, 500 MHz Bandwidth.

OUTPUT: Real Time Phased Sum of 8antennas spooled to Mark Vb VLBI datastorage unit.

Build a scalable system using state of artsampling and FPGA technology.

Why FPGAs?

Field Programmable Gate Arrays → Like aPLA but can do much more!

FPGA ASICShort development cy-cle.

Long cycles

High cost. Low cost for large vol-umes.

Reconfigurable Use or throw.Design can be up-graded

Designs carved in sili-con.

Partners

(1) CASPER team at UC Berkeley led by DanWerthimer building FPGA based radioastronomy signal processing technology.

Partners

(2) MIT/Haystack using (1) to build DigitalBack End (DBE) for Mark Vb VLBI storageequipment.

Partners

(2) MIT/Haystack using (1) to build DigitalBack End (DBE) for Mark Vb VLBI storageequipment.

Let us use (1) combine with (2), customizeand build the SMA beam former.

CASPER Technology

iBOB Board based onXilinx Virtex II Pro.Heart of SMA PhasedArray Processor

CASPER Technology

iADC boards plugdirectly into iBOBs andprovide high speedsampling.

CASPER Technology

iADC boards plugdirectly into iBOBs andprovide high speedsampling.

Other boards which wedidn’t need → BEE2CASPER flagship.

iBOB-iADC

Atmel ADC

(AT84AD001),

2Gsamples/sec or

1Gsample/sec

iBOB-iADC

Atmel ADC

(AT84AD001),

2Gsamples/sec or

1Gsample/sec

Xilinx Virtex II

Pro. 5MB SRAM,

≈ 50K logic cells,

2 PPC, Rocket

iBOB-iADC

Infiniband, VSI,

RS-232, 100BaseT

Ethernet, External

iBOB-iADC

Infiniband, VSI,

RS-232,

100BaseT

Ethernet, External

Symbolic Repre-

sentation.

BEE Design Flow

VHDL → Low

BEE Design Flow

VHDL → Low

Simulink → Higher

BEE Design Flow

VHDL → Low

Simulink → Higher

Fixed Platform →

Details hidden in

design flow

BEE Design Flow

VHDL → Low

Simulink → Higher

Fixed Platform →

Details hidden in

design flow

Berkeley Libraries:

Interface, Radio

Astronomy

Mark Vb DBE

ADC 4x8bits

1024Mhz

256MHz

FourierTransform32 point

Gain Adjustper bin

VSIBusInterface

Mark Vb Recorder

Infiniband Link

iADC iBOB

Time Domain Frequency Domain

Analog InFromDownconverter

iBOB Based Mark Vb Re cording Interface

VLBI Station 1

MarkVb

Single Baseline Phased Array

Delay adjust.(Geo,Atm,Inst)

MixMixLO LO

φ1φ2

φ1 − φ2

Delay andphase adjust.

MixMixLO LO

φ1φ2

φ1 − φ2

Delay andphase adjust.

Delay andphase adjustwith fringerotation.

IF Subsystem

0.5 GHz 1.5 GHz1 GHz

SMA 1st DCV Block Filters (MHz)

528768 1008

10401280 1520

1024 MHz1024 MHzMM

Phased Array Processor

M5 Recorder

VLBI IniBOB-1

iBOB-2

≈ 8 Gbps per antenna

M5 Recorder

VLBI IniBOB-1

iBOB-2

8 Gbps

Time Domain Approach

Delay τ1

Delay τ2

Delay τ3

Delay τn

Simple

Accuracy:τmin <<Tsample

Cannot adjustphase

Frequency Domain Approach

φ adjust

Complex

Accuracy:

N → Large

Can adjust phase,

hence LO phase

compensate and

fringe rotation can

be done digitally.

Average

Chunk FilterBW=480MHzCenter=760MHz

or Center=1280MHz

4x1024Mhz

1024Mhz

8bits Digital DelayLineAccuracy 0.1ns

Xilinx Virtex II Pro vp50iADC 2

iADC 1

Antenna 1Polarization P

Polarization P

Antenna 2

Antenna 3

Antenna 4

Demux by 4

256MHz

Digital DelayLineAccuracy 0.1ns

Delay Control

256MHz

10bits

1024Mhz

To Infinibandconnector

Ts = 11024MHz

≈ 0.99ns

τmin = Ts

≈ 0.1ns

Coarse Delay

CONCAT32bits

RD_PTR

WR_PTR

LOGICDELAY

Max Delay4000 ns

Delay Precision4 ns

Control via PPC.

Delay ↑. 4samples repeat.

Delay ↓. 4 sam-ples skipped.

Fine Delay

9101112

32bits

CONCAT

12345678

23DATA

SELECT

Barrel SelectorArrangement

Delay Precision1 ns

Super Fine Delay

1 2 3 4 5 6 7 8 9 10−0.4

−0.2

Sample

Digital Filter for Delay

y(n) = x(n − D)

Hi(z) = z( − D)

hD(n) =sin π(n−D)

π(n−D)

If D is fractional hD(n) becomes afractional delay filter.

FIR approximations of Fractional Delayfilters are not symmetrical.

Precompute Coefficients for fractionaldelays from 0.1 ns to 0.9 ns in steps of0.1 ns.

Load coefficients on demand and imple-ment real time FIR filter using 10 taps.

Super Fine Delay

1 2 3 4 5 6 7 8 9 10−0.4

−0.2

Sample

Digital Filter for Delay

y(n) = x(n − D)

Hi(z) = z( − D)

hD(n) =sin π(n−D)

π(n−D)

If D is fractional hD(n) becomes afractional delay filter.

FIR approximations of Fractional Delayfilters are not symmetrical.

Precompute Coefficients for fractionaldelays from 0.1 ns to 0.9 ns in steps of0.1 ns.

Load coefficients on demand and imple-ment real time FIR filter using 10 taps.

Super Fine Delay

DATA IN

DATA OUT

C1 C2 C3 C4 C5

z−1z−1z−1z−1z−1

Complex designof demux-by-4FIR filter

4 Multiplicationsand 4 partialsums computedin every stage

No. of stages =

No. of Taps

Super Fine Delay

s2s2s2

s3 s3s3s3

s4s4 s4s4s4

s5s5s5s5s5

s6s6 s6s6

s7s7s7

Complex designof demux-by-4FIR filter

4 Multiplicationsand 4 partialsums computedin every stage

No. of stages =

No. of Taps

It Works too!

0 10 20 30 40 50 60 70 80 90 100

Sample

Channel 0

0 10 20 30 40 50 60 70 80 90 100−30

Sample

Channel 1

0 10 20 30 40 50 60 70 80 90 100−30

Average

It Works too!

−50 −40 −30 −20 −10 0 10 20 30 40 50

−0.5

Correlation

It Works too!

0 10 20 30 40 50 60 70 80 90 100

Channel 0

Sample

0 10 20 30 40 50 60 70 80 90 100

Channel 1

Sample

0 10 20 30 40 50 60 70 80 90 100

Average

Sample

It Works too!

−140 −120 −100 −80 −60 −40 −20 0 20

−0.8

−0.6

−0.4

−0.2

Correlation

It Works too!

−60 −58 −56 −54 −52 −50

Correlation

How to get delays?

Geometry → knownwell enough.

How to get delays?

Atmosphere → needto track

How to get delays?

Noisy Data.

How to get delays?

Noisy Data.

SMA Correlator?

How to get delays?

SMACORRELATOR

SMAPHASEDARRAY PROCESSOR

ANT 1ANT 2ANT 3ANT 4

τ1τ2τ3τ4

τ5τ6τ7τ8

Noisy Data.

SMA Correlator?

Instrumental →different paths.

How to get delays?

SMACORRELATOR

SMAPHASEDARRAY PROCESSOR

ANT 1ANT 2ANT 3ANT 4

τ1τ2τ3τ4

τ5τ6τ7τ8

Noisy Data.

SMA Correlator?

Instrumental →different paths.

Another Correlator?

What sort of Correlator?

7 Delay measurements.

δτ is small! Order of few minutes.

Time Multiplex 7 Measurements.

Single Baseline Correlator!

Berkeley Library.

Correlator

PFB FFT

DATA_IN

RS_232

DATA_OUT

Correlator

PFB FFT

DATA_IN

RS_232

DATA_OUT

64 Complex/32Real Channel

Correlator

PFB FFT

DATA_IN

RS_232

DATA_OUT

Use PFB-FFTfrom CASPER.

Correlator

PFB FFT

DATA_IN

RS_232

DATA_OUT

Lots of challenges→ lots of time.

Correlator

PFB FFT

DATA_IN

RS_232

DATA_OUT

Full frequencyoperation.

Correlator

PFB FFT

DATA_IN

RS_232

DATA_OUT

Dynamic Range.

Correlator

PFB FFT

DATA_IN

RS_232

DATA_OUT

Dynamic Range.

Sensitivity

Does it work?

Figure 1: Autocorrelation Vinayak Nagpal, CTH – p. 25/28

Does it work?

Figure 2: SNR = − 2dB Vinayak Nagpal, CTH – p. 25/28

Does it work?

Figure 3: SNR = − 9dB

Does it work?

−500 −400 −300 −200 −100 0 100 200 300 400 5000

−500 −400 −300 −200 −100 0 100 200 300 400 500−3

Figure 6: No Delay Vinayak Nagpal, CTH – p. 25/28

Complete Picture

M5 Recorder

VLBI IniBOB-1

iBOB-2

8 Gbps

Correlator

More work needed!

XAUI Linkintegration

DBE interface

CorrelatorSensitivity

Automatic delayextraction

Fringe Rotation

Bandwidth

Conclusion

The SMA Phased Array Processordevelopment has come a long way.

Most major blocks are ready and working.

Still some work is needed before the systemcan be ready for a sky observation.

Latest trends in FPGA technology and theCASPER paradigm are effective in makingdevelopment cycle times shorter!

Acknowledgements

SMA Team: Jonathan Weintroub, Bob Wilson,John Test, Taco, Jim Moran, Ray Blundell,Lincoln Greenhill.

CASPER Team: Dan Werthimer, Melvyn Wright,Aaron Parsons, Pierre Droz, Henry Chen,Patrick Crescini.

MIT/Haystack: Shep Doeleman, Brian Fanous,Alan Rogers, Alan Whitney.

Jon Conway: Onsala Space Observatory, Sweden.

Xilinx Inc.

Synopsys Inc.Vinayak Nagpal, CTH – p. 28/28

An FPGA based Phased Array Processor for the Sub ...jweintro/vlbi/forbob/Vinayaks Graphics... · An...

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