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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Topics
Buses and networks-on-chips. Networks-on-chips. Data paths. Subsystems as IP.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus-based systems
A bus is a common connection:
box1 box2 box3
ctrldata
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus circuits
Cannot support full connectivity betweenall data path elements must choosenumber of transfers per cycle allowed.
A bus circuit is a specialized multiplexer circuit.
Two major choices: pseudo-nMOS, precharged.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Pseudo-nMOS bus circuit
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Precharged bus circuit
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Asynchronous timing constraints
Must satisfy setup, hold times.
adrs
Setup timeHold time
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus system design
Requirements: Imposed by the other side of the system.
Constraints: Imposed by this side of the system.
a b
requirements
constraints
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
ba
Views of the bus
Hardware:
D Q D Q
Combinationallogic
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Views of bus system, contd.
Timing diagram:
ba
D Q D Q
Combinationallogic
x
y
x y
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus protocols
Basic transaction: four-cycle handshake.
a
b
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Handshake machine
Each side is an FSM (possiblyasynchronous):
a b0 1
Go
ack ack
enq
0 1
enq
ack
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Basic protocols
Handshake transmits data:
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Box 1 logic
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Box 2 logic
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus timing
td1 = d stable
td2 = d not stable
tc1 = c rises
tc2 = c falls
tack1 = ack rises
t1 = t c1 - td1 >= t r
t2 = t ack1 - tc1 >= t h
t3 = t c2 - tack1 >= t h
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Busses and systems
Microprocessor systems often have several busses running at different rates:
CPU
bridge
mem
I/O
High-speed
Low-speed
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Basic signals in a bus
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Bus characteristics
Physical Connector size, etc.
Electrical Voltages, currents, timing.
Protocol Sequence of events.
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Advanced transactions
Multi-cycle transfers: Several values on one handshake.
May use implicit addressing.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
PCI bus
Used for box-level system interconnect. Two versions:
33 MHz. 66 MHz.
Supports advanced transactions.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Multi-rate systems
Logic blocksrunning at different
clock rates maycommunicate:
Multi-chip.
Single-chip. Slow bus connects
to fast logic.
Logic 1 Logic 2
100 MHz 33 MHz
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Resynchronization
Use cascaded registers to minimize thechance of using a metastable value.
D Q D Qd dout
f
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Networks-on-chips
NoC is an on-chip interconnectionnetwork.
Bus is simplest case. Many NoCs have multiple stages.
Packet-based NoCs: Nodes connected by links. Packet may be divided into flits (flits are
always of equal size, packets may not be).
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Bus electrical model
core i
Length 1
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Bus delay
Major components of delay: Drivers.
Bus backbone. Sink capacitive loads.
Delay formula:
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Crossbar
Crossbar allows anycombination of
connections. Allows arbitrary
multicasting.
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Switch-based crossbar
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Crossbar delay
Switch-based crossbar dominated by buffered transmission line:
Multiplexer-based crossbar delay:
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data path logical organization
Register file s h
i f t e r
memory
constant
addresses Shift control
ALU op
carryout
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Register file porting
Register file is an SRAM. Additional ports add area, increase access
time. But additional ports also reduce number of
cycles required for an operation.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Operand fetch from register file
+
1 port
First cycle
Second cycle
Third cycle
2 portsFirst cycle
First cycle
Second cycle
3 portsFirst cycle
First cycle
First cycle
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Register file tradeoffs
SRAM delay grows approximately linearlyin number of ports.
Driver area grows considerably with added ports.
At least two ports makes sense for data
path through put.
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Data path clocking
Major signals:f 1f 2
precharge s f 1 adrs s f 2
data v f 2
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Typical data path structure
Slice includes one bit of function units,connected by busses:
registers shift ALU bus
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bit-slice structure
Many arithmetic and logical functions can be defined recursively on bits of word.
A bit-slice is a one-bit (or n-bit) segmentof an operation of minimum size to ensureregularity.
Regular logical structure allows regular physical structure.
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Abutting and pitch-matching
Cells in bit-slice may be abuttedtogether requires matching positions on
terminals. Pitch-matching is designing cells to ensure
that pins are at proper positions for
abutting.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data path floorplan
m u x
l a t c h
l a t c h
m u x
c o n s
t a n t
R e g
i s t e r f i
l e
s h i f t e r
A L U
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Data path color plan
cell
VDD
VSS
result
Shifter input
Register file
control
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Subsystems as IP
Standards for subsystems are morecomplex:
More variations. More parameters.
Open Core Protocol (OCP) defines socket
for plug-and-play operation. SPIRIT defines standard documentation
for subsystem IP.
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Wishbone standard
Basic unit is master-slave interface. Defines handshake.
Interface defines CLK, ADRS, DATA,WE, STB, ACK, CYC, RST.
Three types of bus transfers: single
read/write, block read/write,read/modify/write.
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Functional verification
Particularlyimportant for soft IP,
but performed evenfor hard IP.
Compare designmodule against
known good design. QIP metric standard
defines verificationstandards.
goldenreference
IPmodule
-inputvectors
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