Advanced Implantation Detector Array (AIDA): Update & Issues Tom Davinson School of Physics...

Advanced Implantation Detector Array (AIDA):Update & Issues

Tom DavinsonSchool of Physics & AstronomyThe University of Edinburgh

presented byTom Davinson

on behalf of the AIDA collaboration(Edinburgh – Liverpool – STFC DL & RAL)

Prototype AIDA ASIC: Channel Layout

• High (20MeV FSR), intermediate (1GeV FSR) and low gain (20GeV FSR) channels in parallel

• Blocks are sequenced to follow signal’s flow (“left to right”)

• Shaper and peak hold at back end to minimize noise

• 400m x 6mm

400m

~6mm

Preamplifiers + feedback

700pF feedback capacitor

High speed buffer

Fast comparators

Slow comparator

Shapers

Peak Holds + MUX

Prototype AIDA ASIC: Top level design

• Analogue inputs left edge

• Control/outputs right edge

• Power/bias top and bottom

• Prototypes delivered May 2009MPW run100 dies delivered

• Functional tests at STFC RAL OK

Prototype AIDA ASIC: Analogue input and bias reference

Prototype AIDA ASIC: Analogue outputs

Prototype AIDA ASIC

1: Medium Energy (ME) + ME

Input signals (voltage step capacitive-coupled)

Preamp buffered output(Low-Medium Energy Channel)

Trigger output

“Data Ready” signal

Variable medium-energy (ME) event followed after 5us by a second fixed ME event: the energy of the first event (11.75pC, 23.5pC, 35.25pC) does not affect the response to the second (11.75pC).

1: Medium Energy (ME) + ME

Input signals (voltage step capacitive-coupled)

Analog output (peak-hold multiplexed output)

Trigger output

“Data Ready” signal

When the data ready signal is active, the correct value is present at the analogue output (after the hit has been detected and the correct address been fed into the output multiplexer).NB: the test environment is very noisy and that affects the measurements.

2: High Energy (HE) + ME

Three high-energy (HE) events (610pC, 430pC, 250pC) followed by a ME event (28.8pC): the initial HE event does not affect the response to the second.[The roll-of of the L-ME channel preamplifier is due to the HE channel amplifier becoming active: the two are effectively in parallel. Note the Range signal changing status after the HE event]

Input signals (voltage step capacitive-coupled)

Preamp buffered output(Low-Medium Energy Channel)

“Range” signalHigh = high-energy channel active

“Data Ready” signal

2: High Energy (HE) + ME

Analog output (peak-hold multiplexed output)

“Data Ready” signal

Although the low-medium energy channel preamp saturates, the correct value is stored and multiplexed to the Analog Output when the “Data Ready” signal is active.

Preamp buffered output(Low-Medium Energy Channel)

3: High Energy (HE) + ME

Fixed high-energy (HE) event (610pC) followed by three ME events (15pC, 30pC, 45pC): the ASIC recovers autonomously from the overload of the L-ME channel and the second event is read correctly.

Input signals (voltage step capacitive-coupled)

Preamp buffered output(Low-Medium Energy Channel)

“Range” signalHigh = high-energy channel active

“Data Ready” signal

3: High Energy (HE) + ME

First value (constant) given by the High-Energy channel, second by the Medium-Energy channel.

Input signals (voltage step capacitive-coupled)

“Range” signalHigh = high-energy channel active

“Data Ready” signal

Analog output (peak-hold multiplexed output)

Prototype AIDA Mezzanine

3rd September 2009

• 4x AIDA ASICs

64 channels• Design complete• Delivery end-October

30 units

Prototype AIDA FEEM

ult

iple

x

read

out

Digital readout

FPGA, Memory, Gbit

Clock distribution Power SuppliesMezzanine

• Design complete• Production in progress

8 units (4x AIDA, 2x DL DDG, 2x LYCCA)• Delivery w/c 21.9.09

Prototype AIDA FEE:

FEE Assembly Sequence

Prototype AIDA Enclosure

• Prototype mechanical design• Based on 8cm x 8cm DSSSD

evaluate prior to design for 24cm x 8cm DSSSD• Compatible with RISING, TAS, 4 neutron detector

• 12x 8cm x 8cm DSSSDs 24x AIDA FEE cards

• 3072 channels

• Design complete

• Mechanical assembly in progress

Prototype AIDA Enclosure

AIDA Project Timeline

• November/December 2009Systems integration (ASIC+Mezzanine+FEE)Bench tests

• February 2010In-beam tests

• March 2010Design revisions

• April 2010 ASIC wafer runFEE production run

• June 2010Production delivery complete

AIDA Project Information

Project web site

http://www.ph.ed.ac.uk/~td/AIDA/welcome.html

Design Documents

http://www.ph.ed.ac.uk/~td/AIDA/Design/design.html

Technical Design Review v1.1ASIC Project Specification v1.4FEE Specification v1.0

The University of Edinburgh (lead RO)Phil Woods et al.

The University of LiverpoolRob Page et al.

STFC DL & RALJohn Simpson et al.

Project Manager: Tom Davinson

Acknowledgements

This presentation includes material from other people

My thanks to:

Ian Lazarus, Patrick Coleman-Smith, Jonathan Strachan & Paul Morrall (STFC DL)Steve Thomas & Davide Braga (STFC RAL)Zhong Liu (Edinburgh)Dave Seddon, Sami Rinta-Antila & Rob Page (University of Liverpool)