Advanced FPGA Based System Design

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Advanced FPGA Based System Design

Lecture-5-6Introduction to VHDL

By: Dr Imtiaz Hussainimtiaz.hussain@faculty.muet.edu.pk

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Outline

• Introduction to Hardware Description Languages• Recommended Literature• Introduction to VHDL– Design Flow

• EDA Tools• VHDL • Design Examples• VHDL Code Structure• Examples

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Recommended Book

• Circuit Design With VHDL By: Volnei A. Pedroni

e-copy available on imtiazhussainkalwar.weebly.com

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What is Hardware Description Language?

• A hardware description language or HDL is any language for description and design of electronic circuits, and most commonly, digital logic.

• It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.

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What is Hardware Description Language?

• There are two primary purposes for hardware description languages

– Modeling of Digital Circuits: Having a model of the circuit allows for simulation and testing of the design for proper operation.

– Hardware description languages are used as one of the first steps in creating large digital integrated circuits.

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HDLs for Analog Circuit Design

Abbreviation Name Use

AHDL Analog Hardware Descriptive Language

an open analog hardware description language

Verilog-AMS Verilog for Analog and Mixed-Signal

an open standard extending Verilog for analog and mixed analog/digital simulation

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HDLs for Digital Circuit Design• The two most widely-used and well-supported HDL varieties used in industry

are Verilog and VHDL.

Abbreviation Name UseABEL Advanced Boolean Expression

LanguageHardware description language for implementing Boolean expressions

AHDL Altera HDL a proprietary language from Altera

Verilog verification logics most widely-used and well-supported HDL

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HDL for Printed Circuit Board (PCB) Design

Abbreviation Name UsePHDL PCB HDL a free and open source HDL for

defining printed circuit board connectivity

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What is VHDL?• The “V” in VHDL is short of yet another acronym:

VHSIC or Very High-Speed Integrated Circuit. The HDL stands for Hardware Description Language.

• VHDL is a programming language that allows one to

model and develop complex digital systems in a dynamic environment.

• VHDL is intended for circuit synthesis as well as circuit simulation.

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What is VHDL?• A fundamental motivation to use VHDL (or its competitor,

Verilog) is that VHDL is a standard, technology/vendor independent language, and is therefore portable and reusable.

• The two main immediate applications of VHDL are in the– field of Programmable Logic Devices (including CPLDs

and FPGAs) – and in the field of ASICs (Application Specific Integrated

Circuits).

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What is VHDL?

• Once the VHDL code has been written, it can be used either to implement the circuit in a programmable device (from Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for fabrication of an ASIC chip.

• Currently, many complex commercial chips

(microcontrollers, for example) are designed using such an approach.

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Design Flow

• As mentioned in previous slides, one of the major utilities of VHDL is that it allows the synthesis of a circuit or system in a programmable device (PLD or FPGA) or in an ASIC.

• The steps followed during such a project are summarized in this figure.

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Design Flow• We start the design

by writing the VHDL code, which is saved in a file with the extension .vhd and the same name as its ENTITY’s name.

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Design Flow• The first step in the

synthesis process is compilation.

• Compilation is the conversion of the high-level VHDL language, which describes the circuit at the Register Transfer Level (RTL), into a netlist at the gate level.

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Design Flow• The second step is

optimization, which is performed on the gate-level netlist for speed or for area.

• At this stage, the design can be simulated. Finally, a place and-route (fitter) software will generate the physical layout for a PLD/FPGA chip or will generate the masks for an ASIC.

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Design Flow

• Finally, a place and-route (fitter) software will generate the physical layout for a PLD/FPGA chip or will generate the masks for an ASIC.

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EDA Tools

• There are several EDA (Electronic Design Automation) tools available for circuit synthesis, implementation, and simulation using VHDL.

• Some tools (place and route, for example) are offered as part of a vendor’s design suite (e.g., Altera’s Quartus II, which allows the synthesis of VHDL code onto Altera’s CPLD/FPGA chips, or Xilinx’s ISE suite, for Xilinx’s CPLD/FPGA chips).

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EDA Tools

• Other tools (synthesizers, for example), besides being offered as part of the design suites, can also be provided by specialized EDA companies (Mentor Graphics, Synopsis, Synplicity, etc.).

• Examples of the later group are Leonardo Spectrum (a synthesizer from Mentor Graphics), Synplify (a synthesizer from Synplicity), and ModelSim (a simulator from Model Technology, a Mentor Graphics company).

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Translation of VHDL Code into a Circuit

• A VHDL code consists of ENTITY and ARCHITECTURE.

• ENTITY is description of I/O pins (ports) of the circuit.

• ARCHITECTURE describes how the circuit should function.

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Translation of VHDL Code into a Circuit• Consider for example a full adder. • Sum bit is computed as • Cout is obtained from

ENTITY

ARCHITECTURE

incbas

ininout cbcabac ...

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Translation of VHDL Code into a Circuit

• From the VHDL code a physical circuit is inferred.

• However, there are several ways of implementing the equations described in the ARCHITECTURE.

• The actual circuit will depend on the compiler/optimizer being used and, more importantly, on the target technology.

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Translation of VHDL Code into a Circuit

• For instance, if our target is a programmable logic device (PLD or FPGA) then two possible results (among many others) for cout are illustrated in following figures.

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Translation of VHDL Code into a Circuit• On the other hand, if our target technology is an

ASIC, then a possible CMOS implementation, at the transistor level, is that of following figure.

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Circuit Simulation• Following figure contains the simulation results from

the circuit synthesized with the VHDL code, which implements the full-adder unit.

• The input pins (characterized by an inward arrow with an “I” marked inside) and the output pins (characterized by an outward arrow with an “O” marked inside) are those listed in the ENTITY.

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Design Example#1

0

0

1

1

F(x, y, z)

1

0

1

0

z

00

10

10

00

yx

0

0

0

1

1

0

1

0

11

11

01

01

),,(...... zyxFzyxzyxzyx

• Develop VHDL Code for following logic.

Design Examples#2

• Develop VHDL Code for BCD to 7 segment Display.

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VHDL Code Structure• As depicted in following figure, a standalone piece of

VHDL code is composed of at least three fundamental sections:

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VHDL Code Structure: Library Declaration• Contains a list of all libraries

to be used in the design. For example: ieee, std, work, etc.

• A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside a library allows them to be reused or shared by other designs.

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VHDL Code Structure: Library Declaration• To declare a LIBRARY (that is, to make it visible to the design)

two lines of code are needed, one containing the name of the library, and the other a use clause, as shown in the syntax below.

• At least three packages, from three different libraries, are usually needed in a design:– ieee.std_logic_1164 (from the ieee library),– standard (from the std library), and– work (work library).

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VHDL Code Structure: Library Declaration• Their declarations are as follows:

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VHDL Code Structure: ENTITY• An ENTITY is a list with specifications of all input and output pins

(PORTS) of the circuit. Its syntax is shown below.

• The mode of the signal can be IN, OUT, INOUT, or BUFFER.

• IN and OUT are truly unidirectional pins, while INOUT is bidirectional. BUFFER, on the other hand, is employed when the output signal must be used (read) internally.

• The type of the signal can be BIT, STD_LOGIC, INTEGER, etc.

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VHDL Code Structure: ENTITY• Finally, the name of the entity can be basically any name, except

VHDL reserved words.

• Let us consider the NAND gate. Its ENTITY can be specified as:

• The meaning of the ENTITY above is the following: – The circuit has three I/O pins, being two inputs (a and b, mode IN) and

one output (x, mode OUT). All three signals are of type BIT. The name chosen for the entity was nand_gate.

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VHDL Code Structure: ARCHITECTURE• The ARCHITECTURE is a description of how the circuit should

behave (function). Its syntax is the following:

• An architecture has two parts: a declarative part (optional), where signals and constants (among others) are declared, and the code part (from BEGIN down).

• The name of an architecture can be basically any name (except VHDL reserved words), including the same name as the entity’s.

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VHDL Code Structure: ARCHITECTURE• Let us consider the NAND gate again.

• The meaning of the ARCHITECTURE above is the following: – the circuit must perform the NAND operation between the two input

signals (a, b) and assign (‘‘<=’’) the result to the output pin (x). The name chosen for this architecture was myarch.

• In this example, there is no declarative part, and the code contains just a single assignment.

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Example• Figure shows the diagram of a D-type flip-flop (DFF),

triggered at the rising edge of the clock signal (clk), and with an asynchronous reset input (rst).

• When rst =1, the output must be turned low, regardless of clk. Otherwise, the output must copy the input (that is, q <= d) at the moment when clk changes from ‘0’ to ‘1’.

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Example• One thing to remember is that VHDL is inherently

concurrent (contrary to regular computer programs, which are sequential).

• So to implement any clocked circuit (flip-flops, for example) we have to ‘‘force’’ VHDL to be sequential.

• This can be done using a PROCESS, as shown in next slide.

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Process• A PROCESS is a sequential section of VHDL code. It is

characterized by the presence of IF, WAIT, CASE, or LOOP, and by a sensitivity list .

• A PROCESS must be installed in the main code, and is executed every time a signal in the sensitivity list changes.

• Its syntax is shown below.

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Simulation Results

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Example#2

• DFF plus NAND Gate

temp

Hint

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VHDL Code

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Example#3

• DFF plus NAND Gate and reset input

rst

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Example#4

• Multiplexers1 s0 Y

0 0 a

0 1 b

1 0 c

1 1 d

dsscssbssassy ........ 21212121

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VHDL Code

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WHEN/ELSE Command

• Syntax

• Example

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Example#5

• Another way to do it

s1 s0 Y

0 0 a

0 1 b

1 0 c

1 1 d

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VHDL Code

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WITH WHEN/ELSE Command

• Syntax

• Example

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Example#6

• In multiplexer sel could be an integer

sel Y0 a

1 b

2 c

3 dSel(0:3)

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Solution-1: WHEN/ELSE Command

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Solution-2: WITH WHEN/ELSE Command

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Example#7

s2 s1 s0 y0 0 0 S0 0 1 T0 1 0 U0 1 1 V1 0 0 W1 0 1 X1 1 0 Y1 1 1 Z

MUX

Sel(0:7)

y

S

Z

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Example#8

• Multiplexer

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Example#9

• Write down VHDL Code of Multiplexer using WHEN/ELSE and WITH WHEN/ ELSE commands.

Example#10• Develop VHDL Code using WHEN/ELSE and WITH

WHEN/ELSE for BCD to 7 segment Display.

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