Adding a New Dimension to Physical Design · 20 0 20 0 10 0. 15 0. Bandwidth in MB/s . v 4. v 5 3D...

Adding a New Dimension to Physical Design

Sachin SapatnekarUniversity of Minnesota

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Outline

• What is 3D about?

• Why 3D?

• 3D-specific challenges

• 3D analysis and optimization

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3

Planning a city: Land usage[Somewhere in the American midwest; pop. density typically about 20 persons/km2]

[Minneapolis, p.d. = 2,700/km2] [SF= 6,688/km2] [New York=10,600/km2]

Types of 3D circuits

4

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w.ir

vine

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Wafer stackingPCB stacking Memory – vertical TFTs

[Mat

rix S

emic

ondu

ctor

]

Example application

Antenna Layer Antenna Layer

LNA / MixerLNA / Mixer

DownDown--conversion conversion layer:layer: IF,IF,ADC,ADC,DigitalDigitalBasebandBaseband

Digital Digital processing processing

IsolationIsolationplaneplane

BackBack--MetalMetal

Example of a commercial application

5[Beyne, IMEC]

Example 3D processes

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[H. Hedler, ISSCC 2007 Qimonda]

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[IBM]

[Koyanagi, Tohoku U./Zycube]

[Hedler, Qimonda]

Through-silicon vias (TSVs)Keep-out distance

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[Nowak, Qualcomm]

[Tezzarron]

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Schematic of a 3D IC

SOI wafers with bulk substrate removed

Adapted from [Das et al., ISVLSI, 2003] by B. Goplen

Generalized view

Bulk waferMetal levelof wafer 1 Layer 1

Layer 2

Layer 3

Layer 4

Layer 5

Bulk Substrate

Detailed view

Inter-layerbonds

Devicelevel 1

~500µm

~10µm

1µm

Interlayer Via

Outline

• What is 3D about?

• Why 3D?

• 3D-specific challenges

• 3D analysis and optimization

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Another “dimension” to scaling

3D provides an alternative avenue towards increasing system sizes

Orthogonal to device scaling

[Intel]

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3D Interconnects• Reduced wire lengths

• Theoretically– For an L×L 2D chip, max

wire length reduces from 2L to

0

200

400

600

800

1000

1200

1400

0 5 10 15 20 25 30 35

Length (mm)

Net

Den

sity

(#/m

m)

4 Strata2 Strata1 Stratum

3D Global Net Distributions

2D

3D

mL2 L2 Cache

CPU & L1Cache

DRAMDRAMDRAMDRAM

DRAM

Heat Sink

Thermal G

radient

Why are shorter wires good?

• Sequential critical length (“cycle reach”) trends

• Critical interbuffer length also shrinking (i.e., buffer count increasing)

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90nm 65nm 45nm 32nm

M3M60

1234567

Relative critical

seq. length

P6, ~core cycle reach

65nm, ~5.2 GHz

2x wire

4x wire

8x wire

1x wire

[Intel]

[IBM]

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Other benefits• Improved isolation in 3D

– Critical for analog/RF ckts– Lower digital/mixed-signal

noise– Shielding is possible either

using metal layers, or by leveraging bonding material

• Heterogeneous integration– Different layers can be made of

different materials– Can integrate, for example

• CMOS• GaAs• Optical elements (VCSELs)• MEMS/NEMS• Exotic cooling technologies

(micropumps, piezoelectric devices, microrefrigerators)

(Cu)

[Das

et a

l., I

SPD

04]

Outline

• What is 3D about?

• Why 3D?

• 3D-specific challenges

• 3D analysis and optimization

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15

Geometrical challenges

SOI wafers with bulk substrate removed

Adapted from [Das et al., ISVLSI, 2003] by B. Goplen

Generalized view

Bulk waferMetal levelof wafer 1 Layer 1

Layer 2

Layer 3

Layer 4

Layer 5

Bulk Substrate

Detailed view

Inter-layerbonds

Devicelevel 1

500µm

10µm

1µm

Interlayer Via

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Thermal challenges• Each layer generates heat• Heat sink at the end(s)

• Simple analysis– Power(3D)/Power(2D) = m

• m = # layers– Let Rsink = thermal resistance of heat sink– T = Power × Rsink

• m times worse for 3D!

• And this does not account for– Increased effective Rsink– Leakage power effects, T-leakage feedback

• Thermal bottleneck: a major problem for 3DLayer 1

Layer 2

Layer 3

Layer 4

Layer 5

Bulk Substrate

Thermal impact on circuit performance• Gate delays change with T

– Mobility goes down

– Vth goes down

– Which effect wins?– Positive, negative, mixed T

dependency

• Wire delays change with T• Leakage increases with T• Reliability degrades with T

– NBTI, electromigration

• Can use better heat sinks, but…

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The same circuit at various process corners Heat sink cost vs. Power

SiH + h+ → Si+ + ½H2

Si HSi HSi H

H2

Substrate PolyGate Oxide

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Power delivery challenges• Each layer draws current from the power grid• Power pins at the extreme end tier(s)

• Simple analysis– Current(3D)/Current(2D) = m

• m = # layers– Let Rgrid = resistance of power grid– Vdrop = Current × Rgrid

• m times worse for 3D!

• And this does not account for– Increased effective Rgrid– Leakage power effects, increased current

due to T-leakage feedback

• Power bottleneck: a major problem for 3DLayer 1

Layer 2

Layer 3

Layer 4

Layer 5

Bulk Substrate

• Greater challenge in 3D due to via resistance, limited number of supply pins

Power supply integrity in 3D

The Trend of Current per Power Pin from ITRS

0

50

100

150

200

250

300

2005 2010 2015 2020 2025

YearC

urre

nt p

er P

ower

Pin

(mA

)

2D

Pins

3D

Current per power pin (2D) – ITRS

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[Zhan, ICCAD07]

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Yield/test challenges• Yield due to spot defects reduces exponentially with area

– Smaller areas imply better yield– Stack together smaller die; yield improves!– (Note that stacking wafers together does not help!)

• Problem– Need to have known-good die (KGD)– Must test die prior to 3D assembly

• Testing thinned die is hard: mechanically too weak for probe pressure!• Can test die prior to thinning – but then, connections to other layers

are untested!

[Mak, Intel]

Outline

• What is 3D about?

• Why 3D?

• 3D-specific challenges

• 3D analysis and optimization

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Thermal analysis

• Heat generation– Switching gates/blocks act as heat sources– Time constants for heat of the order of ms or more

• Thermal equation: partial differential equation

• Boundary conditions corresponding to the ambient, heat sink, etc.

• Self-consistency– Power = f(T)– T = g(Power)

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0z)y,Q(x,zT

yT

xT

2

2

2

2

2

2=+

∂

∂+

∂

∂+

∂

∂zyx KKK

Thermal solution techniques• Numerical: solve large, sparse systems of linear equations

– Finite difference method: thermal – electrical equivalence• System structure is similar to power grids (good!)

– Current sources ↔ power, voltage ↔ temperature– Finite element method

• Semi-analytical– Green functions (fast, appropriate for early analysis)

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xz

y

heat sources

...

ambient temperature...

wafer

... ...

+~

+~

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Thermal optimization

• Minimize power usage

• Rearrange heat sources

• Improved thermal conduits

• Improved heat sinking Heat Sink

Chip

Rchip

Pcells

Rheat sink

3D floorplanning

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[Zhou, ICCAD07]

3D placement

• Incorporate thermalissues

• Force-directed vs. partitioning methods

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Heat Sink

IOPad 1

Net1

Net3

Net2

IOPad 2

Cell 3Cell 4

Cell 2

Cell 1

Cell 5

TRR Net 1TRR Net 2

TRR Net 3TRR Net 5

TRR Net 4

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Interlayer via count vs. wirelength (ibm01)

0

1000

2000

3000

4000

5000

6000

7000

8000

9000

1 1.5 2 2.5 3 3.5 4 4.5

Inte

rlaye

r Via

s pe

r In

terla

yer

Wirelength, m

10 layers9 layers

8 layers

7 layers

6 layers

5 layers

4 layers

3 layers

10 layers

5 layers4 layers 3 layers

2 layers

1 layer

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z

xy

} Inter-layer} Layer} Bulk Substrate

Inter-RowRegion

Row RegionThermal Via Region

Substrate

Thermal Via

Thermal vias

• Thermal vias– Electrically isolated vias– Used for heat conduction

• Thermal via regions– Contains thermal vias– Predictable obstacle for routing– Variable density of thermal vias

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Temperature profile

Before Thermal Via Placement After Thermal Via Placement

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Thermal via insertion

Thermal Via RegionsTemperature Profile

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3D routing with integrated thermal via insertion

• Build good heat conduction path through dielectric:• Thermal vias: interlayers vias dedicated to thermal conduction.• Thermal wires: metal wires improves lateral heat conduction.• Thermal vias + thermal wires a thermal conduction network.

• Thermal wires compete with lateral signal wire routing.

• Thermal vias: large, can block lateral signal routing capacity.

thermal vias thermal wires

[Zhang, ASPDAC06]

Active cooling techniques

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Fluidic I/OOptical I/O

Optical I/OElectrical I/OFluidic I/O

Si Die

Si microchannel heat sink

Polymer cover

Si

“Trimodal I/O”

TWV

[Bakir, GaTech - CICC 07]

Microfluidic cooling

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Optical waveguideCu wire

Si Die

Trimodal I/Os

TSV-F

TSV-E

Fluidic channel

0

10

20

30

40

50

60

70

80

90

100

0 50 100 150 200 250 300 350

Localized power density (W/cm2)

Tem

pera

ture

rise

on

heat

ers (

C)

Flow rate = 34 ml/minFlow rate = 78 ml/minFlow rate = 104 ml/minFlow rate = 125 ml/min Area: 8 mm2

[Bakir, GaTech]

3D and multicore systems

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[Karnik, Intel]

[Xie, Penn State]

NoCs

3D bus/NoC hybrid

3D NoCs• Need to build custom NoCs for 3D

architectures

• Floorplanning + NoC design

• 3D-specific challenges– Technology constraints, like TSV# – Tier assignment– Placement of switches– Accurate power and delay modeling

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v2v1

v3v4

Core graph

v5

200

200

200

100

150

Bandwidth in MB/s

v4

v5

3D custom NoC architecture

v1

v3v2

tier 1

tier 0

s2

s3

s1

[Zhou, ASPDAC10]

Conclusion

• Numerous challenging problems in 3D IC design• Significant research already in floorplanning, placement,

routing• New challenges in architectural-level issues, NoCs, power

delivery, test

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Thank

You!

Any

Questions?