A Reconfigurable Heterogeneous Microserver Architecture

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A Reconfigurable Heterogeneous Microserver Architecturefor Energy-Efficient Computing

Martin Kaiser, René Griessl, Jens Hagemeyer, Dirk Jungewelter,

Florian Porrmann, Sarah Pilz and Mario Porrmann

Bielefeld University, Germany

Micha vor dem Berge, Stefan Krupop

Christmann IT, Germany

www.m2dc.eu

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Heterogeneous Scale Out Microserver

▪ Combine CPU, GPGPU, FPGA and

hybrid technologies

▪ Provide all architectures in

high-performance and

low-power variants

Data Centers’ Challenges

▪ Computing power

▪ Costs (TCO)

Developers’ Challenge

▪ Select best target architecture

Introduction

x86

GPU

FPGA

?ARM

v8

GPU

SoC

FPGA

SoC

2U / 3U

Chassis

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RECS®|Box – Resource-Efficient Cluster Server

Low-Power

Carrier(up to 16 nodes)

High-Performance

Carrier(up to 3 nodes)

PCIe Expansion

Carrier(1 Accelerator)

RECS Server

▪ up to 15 Carriers

▪ up to 45 High-Performance Microservers

▪ up to 260 Low-Power Microservers

RECS Server Backplane (up to 15 Carriers)

Carrier (PCIe Expansion)Carrier (High Performance)

FPGA-Accelerator

Carrier (Low Power)

x86 ARM v8

#3#2

Microserver(High Performance)

#1

Microserver(Low Power)

#16

#3#2

Microserver(Low Power)

#1

High-Speed Low-Latency Network (PCIe, High-Speed Serial)

Compute Network (up to 40 GbE)

Management Network (KVM, Monitoring, …)HDMI/USB

iPass+ HD

QSFP+

RJ45

GPU SoCFPGA SoC ARM Soc

High-Performance Microserver (COM Express) Low-Power Microserver (Apalis/Jetson)

FPGA SoC

Ext. Connectors

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Custom FPGA Accelerator „RAPTOR-XPress“

▪ 4x Virtex-7 FPGA (XC7VX690T)

▪ Advanced Inter-FPGA communication infrastructure

▪ FPGA-to-FPGA bandwidth: 200 Gbit/s

▪ Board-to-Board bandwidth: 4x 200 Gbit/s

▪ Low-latency: 400 ns (application-to-application)

▪ Support

▪ Direct Kernel-to-Kernel communication between

FPGAs via high-speed serial transceivers

Next generation is developed by

FPGA Acceleration

www.paraxent.com www.trenz-electronic.de

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RECS®|Box – Resource-Efficient Cluster Server

▪ Heterogeneous Microserver

▪ CPU, GPU, FPGA and hybrid technologies

▪ Modules for high-performance and low-power

▪ Configurable and scalable high-speed, low-latency

communication infrastructure

▪ Easy programming via OpenCL

Benchmarks will be published, soon!

Summary

High Performance

Carrier

Application-driven server architecture

FPGA-Acceleration

COM ExpressApalis/Jetson

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A Reconfigurable Heterogeneous Microserver

Architecture for Energy-Efficient Computing

Dipl.-Ing. Martin Kaiser

Bielefeld University, Germany

Cognitronics and Sensor Systems Group

mkaiser@cit-ec.uni-bielefeld.de

www.m2dc.eu