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A 90nm Variable Frequency Clock System for a Power-
Managed Itanium® Architecture Processor
Tim Fischer, Ferd Anderson, Ben Patella, Sam Naffziger
Intel, Fort Collins, CO
Presentation Overview
• Montecito Clock System Architecture• Montecito Voltage to Frequency Converter
(VFC) Architecture– Digital Frequency Divider (DFD)– Regional Voltage Detector (RVD)
• Results• Summary and Acknowledgements
Clock SystemArchitecture
FixedSupply
VariableSupply
Bus Clock
I/Os
Foxton
Bus Logic
Core0
Core1
1/N
CVD
RAD
Gater
1/1
GaterCVD
RVD
DFD
DFD
SLCB CVD GaterPLL
DFD
SLCB CVD Gater
SLCB
DFD
CVD Gater
1/M
DFD
DFD
1/NRAD
SLCB
SLCB
DivisorsFrequency Translation Table
Fuses
PinsBalanced
Tree ClockDistribution
Phase Aligner
Montecito Clock Generation Overview
• PLL generates master clock: Fmax = M*Fbus_clock
• DFDs lock on Fmax using local DLLs– Synthesize core / uncore frequencies in 1.6% Fmax
steps (ticks)– DFD range is Fmax*1.0 to Fmax*0.504– Translation table sets DFD frequency at startup
• Supply / Clock Domains– 2 Cores : variable V, F– Uncore (bus logic): fixed V, F = N * bus clock– Foxton controller : fixed V, F = 1 GHZ, DSP algorithms– Master PLL : fixed V, F, within clock system only
Montecito Clock System Floorplan
PLL / PLL / translation translation table / table / clock clock controlcontrol
FSB FSB DFDsDFDs
Foxton Controller DFDFoxton Controller DFD
FSB FSB DFDsDFDs
Core Core DFDsDFDs
RVDsRVDs
CORE 1CORE 1
CORE 0CORE 0
Bus Logic DFDBus Logic DFD
Clock System Modes• Fixed Frequency (FFM)
– Cores/Uncore are frequency and phase aligned– Cores/Uncore interfaces synchronous
• Variable Frequency (VFM)– Core supply modulated by Foxton Controller to
manage power envelope– Core frequencies track Vcore via Regional
Voltage Detector (RVD) V-F curves• Respond to Foxton modulation and local transients• V-F curves match worst-scaling paths on chip
– Core/Uncore interfaces asynchronous
Voltage-to-Frequency Conversion (VFC)Per Core
DFD1 L1 Clock Route To SLCBS
L0 Clock Route from PLL
22
4
RVD4 RVD5 RVD6 RVD7
2
2
DFD2
RVD11
L1 Clock Route To SLCBS
4
RVD9 RVD10
2
8
8
DFD0
RVD3
L1 Clock Route To SLCBS
2
4
RVD0 RVD1 RVD22
8
RVD8
Utility Clocks
Utility Clocks
Utility Clocks
DOWN[11:8], HOLD[11:8]
DOWN[3:0], HOLD[3:0]
DOWN[7:4], HOLD[7:4]
+
Local Blocks
di/dt noise
VDD
Foxton-managed VDD from VR
Process,Temp
~2400um
RVD8 local environment
Increased delay asserts period “UP” for two cycles
Example VFC Supply Droop Response
DFD Output Clock
Vcore
RVD Delay Line Clock
Period “UP” to DFD
Clock period increased No Adjust needed this cycle
Droop increases RVD delay line delay
1 2 3 4 5
Digital Frequency Divider (DFD) Block Diagram
PLL CLOCK DIFFERENTIAL INPUT
64 PHASES
STATE MACHINE
FULL FREQUENCY DIFFERENTIAL “UTILITY” CLOCK ROUTES TO CLOCK SYSTEM
PCSM
PERIOD ADJUST +2 TO -1
16-PHASE DLL AND INTERPOLATION
TO / FROM SAME-CORE PCSMS
STARTUP CONTROL
RVD UP / DOWN REQUESTS
DIVIDE BY 2
DIVIDE BY 2
ODCS CONTROL
SCAN AND TRIGGERS
½ FREQUENCY QUADRATURE DIFFERENTIAL CLOCK ROUTES TO SLCBS
DFD Phase Selection Datapath
I
O
I
I
4:1 PHASE OR& CLOCK DRIVE
FROMDLL
FROMPCSM
FROMS/M
4:1 PHASEADJUST
16:1 PHASE SELECTION
rckVDD
adj3
psel3
VDD
fb_terms
sel1
phs1
sel7
phs7
VDD
sel8
phs8
sel9
phs9
sel15
phs15
GND GND
pd
GND
GND
VDD
VDD
pd1
GND
pd0sel0
phs0
GNDVDD
adj0
psel0
GND
clk_
63_4
8_ou
t
clk_
15_0
_out
clk_
47_3
2_ou
t
clk_
31_1
6_ou
t
CLO
CK
VFC/RVD Voltage Tracking andCMOS Critical Path Scaling
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
600 800 1000 1200
Supply Voltage (mV)
Del
ay (n
orm
to 1
100
mV
)
circuit1circuit2circuit3circuit4circuit5
RVD Block Diagram
Delay Line 0A
Delay Line 1A
Delay Line 0B
Delay Line 1B
RV
D F
SM
dly0in
dly1in
HOLD
DOWN
dly0out
dly1out
eval0
eval1eval0
eval1clk
additional delay CVDs create deadzone
eval1
eval0
RVD Delay LineFINE
in R R
COARSE
R RRR RR R
0 1 2 3 4 5 6 7
Dynamic Mux
delay line out
odd
coarse_sel
F FF F F F F F F
Coarse Delay Incremental Curves Fine Delay Incremental Curves
4.00E-10
5.00E-10
6.00E-10
7.00E-10
8.00E-10
9.00E-10
1.00E-09
1.10E-09
1.20E-09
1.30E-09
0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40
4 Coarse Elements
3 Coarse Elements2.00E-10
4.00E-10
6.00E-10
8.00E-10
1.00E-09
1.20E-09
1.40E-09
1.60E-09
0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40
RVD Coarse Delay Element
I
O
I
I
I
I I
I
Metal 1 Serpentine Resistor
out
VDD
nout
nrun
run
nrunfbn
runfbp
GND
VDD
even
clear
GND
nrun fetconfig_fet nfet
nrunrun
GND
VDDfbp
nclear
nodd
in
nfet
RVD Phase Comparator
I
O
I
I
I
I
I
nd1ev0 nd0
rckVDD
noh outin1in0
ev1
eck
GND
0
2
4
6
8
10
0 20 40 60 80 100 120Supply Noise (mV)
VFM
Per
form
ance
Incr
ease
(%
)
Average(50 MHzNoise)
Peak
0 500 1000
1.01
1.02
1.03
1.04
1.05
1.06
1.07
Time (ps )
Vco
re
0 500 1000
1.01
1.02
1.03
1.04
1.05
1.06
1.07
Time (ps )
Vco
re
2
4
6
8
10
12
14
16x 10
-3
VFM Performance vs. Supply Noise
b)
a)
c) 10-1
100
101
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
Frequency (GHz)
PS
D (d
BV
)
50% Activity Power Virus
FFM/VFM Core/Bus Clock Oscilloscope Traces
FFM, 1.2V
VFM, 1.2V
Core clock 1.6GHz
Bus Logic clock 1.6GHz
Core clock 2.14GHz
Bus Logic clock 1.6GHz
Core Clock Spectral Content
FFM
Fmax=2GHz, Ffixed=1.6GHz, 1.2Vcore
VFM
Fmax=2GHz, 1.2 Vcore +/- 100mV, slow RVD curve
Summary• Clock system enables a dynamic voltage-scaling power
management system (Foxton)– Generates low-skew fixed- and variable- frequency clocks
• High-BW Voltage-to-Frequency conversion (VFC)– Regional Voltage Detectors– Synchronized Digital Frequency Dividers– VFC follows programmed V/F response– VFC lock onto and tracks local supply voltage
• Tracks high-BW switching transients:1 cycle VFC loop response• Tracks low-BW Foxton-based supply modulation
• Performance benefits through reduced guardband:– Fast response to switching transients (3-8%, path dependent)– Tracks process, temperature (3%)
• VFM operation demonstrated above 2GHz
AcknowledgementsE. Fetzer, S. Ghahremani, B. Doyle, A. Barton, M. Peters, S. Hall, J. Desai, E. Lee, F. Verdico, C. Pie, C. Bendele, A. Allen, R. Alley, P. Wyatt, B. Johnson, S. Undy, G. Benjamin, R. McGowen, R. Sandoval, C. Zhu, C. Young, A. Shoning, J. McBride, K. Kerr, D. Newsome, D. Sherlock, B. Haskin, J. Platenak, A. Gouldey, V. Freytag, R. Sims, G. Kumar, J. Pettsinger, R. Weidner, P. Liu, S. Wells, D. Clifford, S. Liepe, J. Ignowski, G. Ranson, P. Kummrow, C. Keen, W. Kever
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