3 Instruction cycle

3 Instruction cycleBikash Chhetri

• 3.1 Instruction cycle, Machine cycle and T-state

• .3.2 Machine cycle of 8085 Microprocessor

• 3.2.1 Op-code fetch Machine cycle

• 3.2.2 Memory read Machine cycle

• 3.2.3 Memory Write machine Cycle

• 3.2.4 I/O read machine cycle

• 3.2.5 I/O write machine cycle

• 3.3 Timing diagram of MOV, MVI, IN, OUT, LDA, STA

Content

• Instruction:- An instruction is a command given to the processor to perform a specified operation on a given data which is known as instruction.

• Program:- To perform a particular task, a programmer write a sequence of instruction called a program.

• Note:- Program and Data are stored in the memory. The cpu fetches one instruction from the memory at a time and execute it.

3.1 Instruction cycle

• Instruction cycle:- The time taken for executing an instruction is called instruction cycle.

• An instruction cycle consists of 2 parts:-

Instruction Cycle

1. Fetch Cycle 2. Execution cycle

3.1 Instruction cycle

• Note:- Instruction cycle(IC) = Fetch cycle(FC) + Execution Cycle(EC)

Fetch Cycle:-

1. A CPU fetches opcode or the machine code of an instruction from memory where 1st byte of an instruction is its opcode.

2. An instruction may be more than one bytes long the other bytes are data or operand address.

3.1 Instruction cycle

Memory Processor Instruction

register

1. If an instruction contains data or operand from the memory, then the processor has to perform read operation to get the data.

2. Then, Execution process starts, In EC read or write operation from memory to M.P or from microprocessor to memory is done.

3.1 Instruction cycle

EXECUTION CYCLE:-

1. OPCODE:- Opcode tell the m.p which operation to perform.

Example:- ADD, SUB etc.

2. Operand:- Operand are the data contents on which the operation is to be performed.

Opcode and Operand

MOV A, B

Opcode

Operand

1. To execute an instruction, the m.p communicates with memory, I/O and other peripheral devices. When the processor communicates with peripherals devices it is called machine cycles.

1. During this , the address, the data, controls and status signals are exchanged between m.p and peripherals devices.

3.1 Machine Cycle

• The graphical representation of the steps of a machine cycle is called Timing Diagrams.

3.1 Timing Diagrams

There are 5 machine cycle in an 8085 m.p:-

1. Opcode fetch machine cycle

2. Memory Read machine cycle

3. Memory write machine cycle

4. I/O Read machine cycle

5. I/O write machine cycle

3.2 Machine Cycle of 8085 microprocessor

1. In Opcode fetch machine cycle, the m.p fetches the opcode of an instruction from memory.

2. It has 4 T-States.

3.2.1 Opcode fetch machine cycle

CLOCK CYCLE T 1:

1. During the 1st clock cycle T1, microprocessor sends out the address of the memory location where opcode is available.

2. The MSB of address is placed on the address lines A8-A15. LSB of address is placed on the address/data bus. Lines AD0 –AD7 and the ALE signals goes high.

3. The IO/M signal goes low to indicate that it is a memory operation.

4. The status line S0 and S1 are both high to indicate an opcode fetch operation.

CLOCK CYCLE T 2:

1. In clock cycle T2, the control unit sends the active low control signal RD to enable the memory chip.

2. The RD signal remains active low for two clock cycle T2 and T3.

3. The opcode byte is placed on the data bus AD0 –AD7 from the memory location.

CLOCK CYCLE T 3:

1. At the end of T3 clock cycle, the RD signal goes high forcing the bus to enter into high impendence.

CLOCK CYCLE T 4:

1. The opcode byte is placed in the instruction decoder of the microprocessor and the task is carried out according to the instruction.

2. Normally four clock cycles are required for opcode fetch i.e. T1,T2,T3 and T4.

3.2.2 Memory Read machine cycle

• At time period T1, the higher order memory address is placed on the address lines A15 –A8. When ALE is high, the lower address is placed on the bus AD7 –AD0. The status signal IO/M(bar) goes low indicating the memory operation and two status signals S1 = 1, S0 = 0 to indicate memory read operation.

• At time period T2, the MP sends RD(bar) control line to enable the memory read. When memory is enabled with RD(bar) signal, the data from the addressed memory location is placed on the data bus with ALE low.

• The data is reached at processor register during T3 state. When data is arrived, the RD(bar) signal goes high. It causes the bus to go into high impedance state.

3.2.3 Memory Write machine cycle

• At time period T1, the higher order memory address is placed on the address lines A15 –A8. When ALE is high, the lower address is placed on the bus AD7 –AD0. The status signal IO/M(bar) goes low indicating the memory operation and two status signals S1 = 0, S0 = 1 to indicate memory write operation.

• At time period T2, the MP sends WR(bar) control line to enable the memory write. When memory is enabled with WR(bar) signal, the data from the processor is placed on the addressed location with ALE low.

• The data is reached at memory location during T3 state. When data is reached, the WR(bar) signal goes high. It causes the bus to go into high impedance state.

3.2.4 I/O read machine cycle

• In I/O read machine cycle data from a input port is stored in the accumulator.

• The IO/M signal is made high indicating input/output operation.

3.2.5 I/O Write machine cycle

• The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system.

• The processor takes, 3T states to execute this machine cycle.

3.3 Timing Diagram

1. MOV

2. MVI

3. IN

4. OUT

5. LDA

6. STA

1. MOV A,B

The instruction MOV A,B is a 1-byte instruction. Microprocessor takes only one machine cycle (op-code fetch) to complete instruction. Hence, hex code for MOV A,B is passed to the microprocessor.

2. MVI B,43H

This instruction is 2-byte instruction. Microprocessor takes two machine cycles (one is op-code fetch cycle for MVI B and another is memory read cycle for immediate data i.e. 43H) to complete the instruction.

Fetching the Op-code 06H from the memory 2000H. (OF machine cycle)

Read (move) the data 43H from memory 2001H. (memory read)

3. IN

• Fetching the Opcode DBH from the memory 4125H.

• Read the port address C0H from 4126H.

• Read the content of port C0H and send it to the accumulator.

• Let the content of port is 5EH.

4. OUT 07H

5. LDA

STA 526AH

1. STA means store accumulator:- The content of the accumulator is stored in the specified address(536A).

2. The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH :- OF machine cycle.

3. Then the lower order memory address is read(6A) :- Memory read machine cycle.

4. Read the lower order memory address(52) :- Memory read machine cycle

5. The combination of both the addresses is considered and the content from accumulator is written in 526A :- Memory write machine cycle.

6. Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A.

STA

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