2.6 GHz Receiver for On-Chip Optical Networking in 65nm ... · 2.6 GHz Receiver for On-Chip Optical...

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

Letizia Fragomeni*, Fabio Agostino*, Alberto Scandurra#, Francesco G. Della Corte*

* DIMET - ‘Mediterranea’ University of Reggio Calabria# STMicroelectronics - On Chip Communication Systems, Catania, Italy

E-mail: letizia.fragomeni@unirc.it

ICECS 2010, Athens, Greece, December 12-15, 2010

ICECS 2010, Athens, Greece

Agenda

ONoC - Optical Network on-Chip: outline

CMOS optical receivers at a glance

Receiver architectureCircuits designSome results

Overcome AGC and AOC issueMultiple thresholds decision circuit

Conclusion

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

1ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

Metal wires limitations:

crosstalklatencyglobal throughput

Optical interconnects integrated in standard CMOS processes

viastack

III-V laser sourceIII-V photodetector

Si photonic waveguide (n=3.5)

SiO2 waveguide cladding (n=1.5)III-V input

waveguidep-contactn-contactabsorption

layer

copp

erin

terc

onne

ctla

yers

CMOS transistor layer

p-contactn-contact

active layerviastack

III-V laser sourceIII-V photodetector

Si photonic waveguide (n=3.5)

SiO2 waveguide cladding (n=1.5)III-V input

waveguidep-contactn-contactabsorption

layer

copp

erin

terc

onne

ctla

yers

CMOS transistor layer

p-contactn-contact

active layer

ONoC – Optical Network on-Chip: outline

WADIMOS –Wavelength

division multiplexed photonic layer on CMOS

ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

CMOS Optical Receivers at a glance

Han et al., A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13µm CMOS, IEEE Transactions on Circuits and Systems-II, Vol. 57, No. 5, May 2010

2

CG-TIA with inductive peaking

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

ICECS 2010, Athens, Greece 3

Variations of input signal

reduced TIA gainnonlinearity effectschanges of signal offset

CMOS Optical Receivers at a glance:AGC and AOC issue

Automatic Gain Control circuits

Automatic Offset Control circuits

Settling time!!!

Han et al., A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13µm CMOS, IEEE Transactions on Circuits and Systems-II, Vol. 57, No. 5, May 2010

4ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

Receiver architecture

Rf: 1.2kΩ polysilicon resistor

ST65nm CMOS technology

5ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

Receiver architectureBias circuits

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

ICECS 2010, Athens, Greece 6

Some simulation results

Iin= 2µApp

In = 7.3pA/Hz-1/2

P@1V = 2.6mW

7

Hp: routed packet of data has a start bit of high logical value and a given length.

and the signal i is the only valid.

Multiple thresholds decision circuit

kSinjS III __ <<

LOHO kbjb == __ ;

1;,...,1;,...,1 >+== inikij

ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

8

ni

OIOOI

CIO

tOtOtV

nbnctrlibibictrl

ctrlictrlictrl

n

iictrlibout

,...,1

;

;

)()()(

__1___

__

1__

=

=+=

⋅=

×=

+

=∑

The correct system output Vout is stated by the following function:

Multiple thresholds decision circuit

ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

9

Multiple thresholds decision circuit

ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

10

Multiple thresholds decision circuit

AIAIAIAI SSSS µµµµ 18,12,6,7.1 4_3_2_1_ ====

ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

11

Conclusion

ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

A CMOS 65nm optical receiver with full rail-to-rail output swing has been discussed

The circuit allows to correctly amplify a 2µApp input current at 4Gbit/s data rate

An instantaneous response multiple decision thresholds output stage for improving the robustness of the system with respect tooffset variations has been proposed

The receiver architecture is well suited for use in optical networking applications

Thank you!

ICECS 2010, Athens, Greece

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

2.6 GHz Receiver for On-Chip Optical Networking in 65nm CMOS Technology

Letizia Fragomeni*, Fabio Agostino*, Alberto Scandurra#, Francesco G. Della Corte*

* DIMET - ‘Mediterranea’ University of Reggio Calabria# STMicroelectronics - On Chip Communication Systems, Catania, Italy

E-mail: letizia.fragomeni@unirc.it

ICECS 2010, Athens, Greece, December 12-15, 2010