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10 December 2012Clive “Max” Maxfield
All ProgrammableFPGAs, SoCs, and 3D ICs
Part V. Advanced Concepts and Future Trends
1
Programmable Analog
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Programmable Analog
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High-Speed Serial Interconnect
4
Clock Recovery
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8-bit/10-bit (8b/10b) Encoding
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Pre-Emphasis and Equalization
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Additional Considerations Multiple Standards• Fibre Channel• InfiniBand• PCI Express (PCIe)• RapidIO• SkyRail• 10 Gigabit
Ethernet• JESD204B• etc.
Increasing Speeds• 3.xxx Gbps• 6.xxx Gbps• 10.xxx Gbps• 28.xxx Gbps
(28nm)• 40.xxx Gbps
(20nm)• 56.xxx Gbps
(14nm)• Optical
(10nm)8
Before 3D ICs
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Before 3D ICs (cont.)
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Before 3D ICs (cont.)
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Early 3D ICs
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Early 3D ICs (cont.)
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Dice on SIP Substrate
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Dice on Silicon Interposer
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Die on Die
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A Brave New World
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State-of-the-Art Today
Homogeneous
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State-of-the-Art Today (cont.)Heterogeneous
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Rad-Hard, Rad-TolerantWhat exactly is radiation?• Ionizing versus non-ionizing• Particles (α, β, Protons, Neutrons, Heavy
Ions)• Rays (X-Rays, Gamma Rays, Cosmic
Rays…)
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Rad-Hard, Rad-TolerantWhere can effects occur• On-chip registers and SRAM memory
cells• On-chip combinatorial logic• On-chip clock buffers• On-chip configuration cells• Off-chip general-purpose memory• Off-chip configuration memory
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Rad-Hard, Rad-TolerantCommon radiation-induced problems• SEE/SEP (Single Event
Effects/Phenomenon)• SEL (Single Event Latchup)• SEU (Single Event Upset)• SET (Single Event Transient)• SEFI (Single Event Functional Interrupt)• Speed degradation
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Rad-Hard, Rad-TolerantMitigation Strategies• Silicon-level (trenches, epitaxial layer)
• LPT (latchup protection technology) circuit• Using special configuration cells
• TMR (triple modular redundancy)• Delaying combinatorial signals• Designing fail-safe state machines• Lock-step dual processor architectures• Design to accommodate speed degradation
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More Information / Further Readingwww.AllProgrammablePlanet.c
om
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