1 Hamming Code, K-maps-Multiplexer Midterm 1 Revision Prof. Sin-Min Lee Department of Computer...

1

Hamming Code, K-maps-MultiplexerMidterm 1 Revision

Prof. Sin-Min Lee

Department of Computer Science

04/19/23 2

Let us play a game !

A volunteer from the audience?

Pick a number, any number, between 1 and 50

04/19/23 3

Is the Number in Here?

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37

39 41 43 45 47 49

04/19/23 4

Is the Number in Here?

2 3 6 7 10 11 14 15 18 19 22 23 26 27 30 31 34 35 38

39 42 43 46 47 50

04/19/23 5

Is the Number in Here?

4 5 6 7 12 13 14 15 20 21 22 23 28 29 30 31 36 37

38 39 44 45 46 47

04/19/23 6

Is the Number in Here?

8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31 40 41

42 43 44 45 46 47

04/19/23 7

Is the Number in Here?

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 49

50

04/19/23 8

Is the Number in Here?

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

49 50

04/19/23 9

And the Number is ….

04/19/23 10

04/19/23 11

Richard Hamming

Richard Wesley Hamming, mathematician, pioneer computer scientist, and professor, died of a heart attack on January 7, 1998, in Monterey, California, at the age of 82. His research career began at Bell Laboratories in the 1940s, in the early days of electronic computers, and included the invention of the Hamming error-correcting codes. In the 1970s he shifted to teaching, and at his death he was Distinguished Professor Emeritus of computer science at the Naval Postgraduate School. He is survived by his wife Wanda, a niece, and a nephew.

04/19/23 12

04/19/23 INFS 515 Digital Logic Level 13

1948: Error Correction

Error-detecting coding, first developed for telephone switching, is now used throughout the computing and telecommunications industries. In 1948 , R.W. Hamming (left) of Bell Labs developed a general theory for error-correcting schemes in which "check-bits" are interspersed with information bits to form binary words in patterns. When a single error occurs in transmission, the word becomes invalid, but the error is automatically located and corrected.

04/19/23 14

04/19/23 INFS 515 Digital Logic Level 15

04/19/23 INFS 515 Digital Logic Level 16

04/19/23 INFS 515 Digital Logic Level 17

04/19/23 INFS 515 Digital Logic Level 18

04/19/23 INFS 515 Digital Logic Level 19

04/19/23 INFS 515 Digital Logic Level 20

04/19/23 21

04/19/23 INFS 515 Digital Logic Level 22

04/19/23 INFS 515 Digital Logic Level 23

04/19/23 INFS 515 Digital Logic Level 24

04/19/23 INFS 515 Digital Logic Level 25

04/19/23 INFS 515 Digital Logic Level 26

04/19/23 INFS 515 Digital Logic Level 27

04/19/23 INFS 515 Digital Logic Level 28

04/19/23 INFS 515 Digital Logic Level 29

04/19/23 30

Truth table to K-Map

A B P

0 0 1

0 1 1

1 0 0

1 1 1

B

A 0 1

0 1 1

1 1

minterms are represented by a 1 in the corresponding location in the K map.

The expression is:

A.B + A.B + A.B

04/19/23 31

K-Maps

• Adjacent 1’s can be “paired off”

• Any variable which is both a 1 and a zero in this pairing can be eliminated

• Pairs may be adjacent horizontally or vertically

B

A 0 1

0 1 1

1 1

a pair

another pair

B is eliminated, leaving A as the term

A is eliminated, leaving B as the term

The expression becomes A + B

32

• Two Variable K-Map

AB

C P

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

A.B.C + A.B.C + A.B.C

BC

A 00 01 11 10

0 1

1 1 1One square filled in for each minterm.

Notice the code sequence: 00 01 11 10 – a Gray code.

04/19/23 33

Grouping the Pairs

BC

A 00 01 11 10

0 1

1 1 1

equates to B.C as A is eliminated.

Here, we can “wrap around” and this pair equates to A.C as B is eliminated.

Our truth table simplifies to

A.C + B.C as before.

04/19/23 34

Groups of 4

BC

A00 01 11 10

0 1 1

1 1 1

Groups of 4 in a block can be used to eliminate two variables:

The solution is B because it is a 1 over the whole block

(vertical pairs) = BC + BC = B(C + C) = B.

Karnaugh Maps

• Three Variable K-Map

– Extreme ends of same row considered adjacent

A BC

00 01 11 10

0

1

A.B.C A.B.C A.B.C A.B.C

A.B.C A.B.C A.B.C A.B.C

0010A.B.C

A.B.C

A.B.C

A.B.C

Karnaugh Maps

• Three Variable K-Map example X A.B.C A.B.C A.B.C A.B.C

A BC

00 01 11 10

0

1

X =

04/19/23 37

The Block of 4, again

A BC

00 01 11 10

0 1 1

1 1 1

X = C

04/19/23 38

Returning to our car example, once more• Two Variable K-Map

A B

C P

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

A.B.C + A.B.C + A.B.C

AB

C 00 01 11 10

0 1 1 1

1There is more than one way to label the axes of the K-Map, some views lead to groupings which are easier to see.

Karnaugh Maps• Four Variable K-Map

– Four corners adjacent

AB CD

00 01 11 10

00

01

11

10

A.B.C.D A.B.C.D A.B.C.D A.B.C.D

A.B.C.D A.B.C.D A.B.C.D A.B.C.D

A.B.C.D A.B.C.D A.B.C.D A.B.C.D

A.B.C.D A.B.C.D A.B.C.D A.B.C.D

A.B.C.D

A.B.C.D

A.B.C.D

A.B.C.D

Karnaugh Maps

• Four Variable K-Map example F A.B.C.DA.B.C.D+A.B.C.DA.B.C.DA.B.C.DA.B.C.DA.B.C.D

AB CD

00 01 11 10

00

01

11

10

F =

41

Product-of-SumsWe have populated the maps with 1’s using sum-of-products extracted from the truth table.

We can equally well work with the 0’s

AB

C00 01 11 10

0 1 1 1

1 1

A B C P

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

AB

C00 01 11 10

0 0

1 0 0 0P = (A + B).(A + C)

P = A.B + A.Cequivalent

04/19/23 42

Inverted K Maps

• In some cases a better simplification can be obtained if the inverse of the output is considered– i.e. group the zeros instead of the ones– particularly when the number and patterns of

zeros is simpler than the ones

Karnaugh Maps• Example: Z5 of the Seven Segment Display

0 0 0 0 1

0 0 0 1 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 1

X1 X2 X3 X4 Z5

1 0 0 1 0

1 0 1 0 X

1 0 1 1 X

1 1 0 0 X1 1 0 1 X1 1 1 0 X1 1 1 1 X

0

1

2

3

4

5

6

7

8

9

0 0 1 0 1X1X2

X3 X4 00 01 11 10

00

01

11

10

Z5 =

• Better to group 1’s or 0’s?

04/19/23 INFS 515 Digital Logic Level 44

04/19/23 INFS 515 Digital Logic Level 45

04/19/23 46

Karnaugh Map Method of Multiplexer Implementation

Consider the function:

A is taken to be the data variable and B,C to be the select variables.

04/19/23 INFS 515 Digital Logic Level 47

Example of MUX combo circuit • F(X,Y,Z) = m(1,2,6,7)

04/19/23 INFS 515 Digital Logic Level 48

49

Implementing the Canonical Sum

• The binary decoder generates all minterms of n-variable logic function.

• The canonical sum ( sum of minterms ) of a logic functions is obtained by adding all minterms of that function:

-Match the order of input bits-Activate Enable inputs

• Example : G2A

Y0

Y1

Y2

Y3

A

B

Z

Y

74x138

Y4

Y5

Y6

Y7CX

G2B

G1

FX Y Z

( , , ), ,

2 4 7F

+5V

50

Design Canonical Form w/ MUX

7) 6, 2, m(1,C)B,F(A,

ABCCABCBACBAC)B,F(A,

F

A0

A1

A2

A3

S1 S0

8-to-18-to-1MuxMux

S2

A4

A5

A6

A7

00

00

00

00

11

11

11

11

Each input in a MUX is a minterm

AA BB CC

51

Design Canonical Form w/ MUX

7) 6, 2, m(1,C)B,F(A,

ABCCABCBACBAF

A B F

0 0

0 1

1 0

1 1

52

Design Canonical Form w/ MUX

7) 6, 2, m(1,F

ABCCABCBACBAF

A B F

0 0 C

0 1 C

1 0 0

1 1 1

F

A0

A1

A2

A3S1 S0

En

4-to-14-to-1MuxMux

AA BB

CC

CC

00

11

Vdd

53

Design Canonical Form w/ MUX

7) 6, 2, m(1,F

ABCCABCBACBAF

B C F

0 0

0 1

1 0

1 1

54

Design Canonical Form w/ MUX

7) 6, 2, m(1,F

ABCCABCBACBAF

B C F

0 0 0

0 1 A

1 0 1

1 1 A

F

A0

A1

A2

A3S1 S0

En

4-to-14-to-1MuxMux

BB CC

AA

AA

Vdd

55

Demultiplexers (DeMux)

F

A0

A1

A2

A3S1 S0

4-to-14-to-1MuxMux

A

D0

D1

D2

D3S1 S0

1-to-41-to-4DeMuxDeMux

56

DeMux Operations

S1 S0 D3 D2 D1 D0

0 0 0 0 0 A

0 1 0 0 A 0

1 0 0 A 0 0

1 1 A 0 0 0

A

D0

D1

D2

D3S1 S0

1-to-41-to-4DeMuxDeMux

ASSD

ASSD

ASSD

ASSD

013

012

011

010

57

DeMux Operations

S1 S0 D3 D2 D1 D0

0 0 0 0 0 A

0 1 0 0 A 0

1 0 0 A 0 0

1 1 A 0 0 0

ASSD

ASSD

ASSD

ASSD

013

012

011

010

D0

D1

D2

D3

A

S1

S0

58

Implementing Functions Using Implementing Functions Using DecodersDecoders

• Example: Full adderS(x, y, z) = (1,2,4,7)

C(x, y, z) = (3,5,6,7)

x

y

z

3-to-8Decoder

S2

S1

S0

0

1

2

3

4

5

6

7

S

C

59

EncoderEncoder

• Function: given 2n inputs, encode the index of input with 1 as the output.

::

noutputs

2n to n

encoder2n

inputs

60

Encoders & Priority EncodersEncoders & Priority Encoders

• Encoders

• Priority encoders

X Y I 0 I 1 I 2 I 3 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1

X Y I 0 I 1 I 2 I 3 1 0 0 0 0 0 x 1 0 0 0 1 x x 1 0 1 0 x x x 1 1 1

Logic functionsX = I0’I1’I2I3’ + I0’I1’I2’I3

Y = I0’I1I2’I3’ + I0’I1’I2’I3

Logic functionsX = I2I3’ + I3

Y = I1I2’I3’ + I3

61

Binary AddersBinary AddersFor example: add 1011012 and 110102,

ie., 4510 + 2610 = 7110

1 1 11 0 1 1 0 1

+ 1 1 0 1 0

_______________________________________1 0 0 0 1 1 1

62

Half AdderHalf AdderTruth table Logic function

63

Full AdderFull Adder

Binary AddersBinary Adders

• Arithmetic Circuit– a combinational circuit for arithmetic operations

such as addition, subtraction, multiplication, and division with binary numbers or decimal numbers in a binary code

• Addition of 2 binary inputs, 'Half Adder‘– 0+0=0, 0+1=1, 1+0=1, 1+1 = 10

S = X'Y + XY' = X Y;

C = XY

Binary AddersBinary Adders• Addition of 3 binary inputs, 'Full Adder'

Logic Diagram of Full Adder

Binary AddersBinary Adders

• Binary Ripple Carry Adder

– sum of two n-bit binary numbers in parallel

– 4-bit parallel adder

A = 1011, B = 0011

Binary AddersBinary Adders

• Carry Lookahead Adder– The ripple carry adder has a long circuit delay

• the longest delay: 2 n + 2 gate delay

Carry Lookahead Adder• reduced delay at the price of complex hardware

– a new logic hierarchy

Pi: propagate function

Gi: generate function

3.8 3.8 Binary AddersBinary Adders

Development of Carry Lookahead Adder