1 COMP541 Sequential Logic Timing Montek Singh Sep 30, 2015

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COMP541

Sequential Logic Timing

Montek Singh

Sep 30, 2015

Topics Timing analysis

flip-flopssequential systemsclock skew

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Input Timing Constraints Setup time: tsetup = time

before the clock edge that data must be stable (i.e. not changing)

Hold time: thold = time after the clock edge that data must be stable

Aperture time: ta = time around clock edge that data must be stable(ta = tsetup + thold)

CLK

tsetup

D

thold

ta

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Output Timing Constraints Propagation delay: tpcq = max time after clock

edge by which output Q is guaranteed to have stabilized (i.e., not changing anymore)

Contamination delay: tccq = min time after clock edge during which Q will not have started changing yetCLK

tccq

tpcq

Q

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Dynamic Discipline The input to a synchronous sequential circuit

must be stable during the aperture (setup and hold) time around the clock edge

Specifically, the input must be stableat least tsetup before the clock edgeat least until thold after the clock edge

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Implications on Design Constrains operation

Given a clock period, constrains circuit delays

Given a circuit, constraints clock periodThe delay between

registers (which impacts clock period) has a minimum and maximum delay, dependent on the delays of the circuit elements

Delays of both comb. logic and flip-flops must be taken into account

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

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Setup Time Constraint Setup time

input to R2 must be stable at least tsetup before the clock edge

constrains max delay from R1 through combinational logic

What’s min clock period?

CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2

What’s min period, Tc?Tc ≥ tpcq + tpd + tsetup

tpd ≤ Tc – (tpcq + tsetup)

So, clock period constrained by:• Delay in CL• Delay in previous reg (R1)• Setup requirement in next reg (R2)

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Hold Time Constraint Hold time

input to R2 must be stable for at least thold after clock edge

constrains the minimum delay from register R1 through the combinational logic

often try to design circuits with 0 hold time requirement

CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2

tccq + tcd ≥ thold

tcd ≥ thold - tccq

If there is no combinational logic between flipflops:

thold ≤ tccq

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Timing Analysis

CLK CLK

A

B

C

D

X'

Y'

X

Y

per g

ate

Timing Characteristicstccq = 30 ps (FF contamination)

tpcq = 50 ps (FF propagation)

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd =

tcd =

Setup time constraint:

Tc ≥

fc =

Hold time constraint:

tccq + tcd > thold ?

tpd = 3 x 35 ps = 105 ps

tcd = 25 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

(30 + 25) ps > 70 ps ? No!

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Fixing Hold Time Violation

per g

ate

CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristicstccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tpd > thold ?

(30 + 50) ps > 70 ps ? Yes!

Add buffers to the short paths:

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Hold Time Often flip-flops are designed for a hold time of

zeroTo avoid these tricky problems

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Clock Skew Clock doesn’t arrive at all registers at the

same timeSkew is the difference between the arrival times of the

clock edge at two different (typically neighboring) flip-flops

Examine the worst case:guarantee that discipline is not violated for any

register pairmany registers in a system!

t skew

CLK1

CLK2

CL

CLK2CLK1

R1 R2

Q1 D2

CLKdelay

CLK

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Setup Time Constraint with Clock Skew Worst case: CLK2 is earlier than CLK1

CLK1

Q1

D2

Tc

tpcq tpd tsetuptskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

Tc ≥ tpcq + tpd + tsetup + tskew

tpd ≤ Tc – (tpcq + tsetup + tskew)

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Hold Time Constraint with Clock Skew Worst case: CLK1 is earlier than CLK2tccq + tcd ≥ thold + tskew

tcd ≥ thold - tccq + tskew

If there is no combinational logic between flipflops:

thold + tskew ≤ tccq

Even if hold time is 0, only a very small skew is tolerated:

tskew ≤ tccq

Next Time Read Section 3.5.1-3.5.3

Next: VGA Monitors Then we’ll move on to memories

Section 5.5

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